/*
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* Copyright (c) 2006 - 2016 Intel Corporation. All rights reserved.
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* Copyright (c) 2005 Topspin Communications. All rights reserved.
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* Copyright (c) 2005 Cisco Systems. All rights reserved.
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* Copyright (c) 2005 Open Grid Computing, Inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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*/
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#ifndef I40IW_ABI_H
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#define I40IW_ABI_H
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#include <linux/types.h>
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#define I40IW_ABI_VER 5
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struct i40iw_alloc_ucontext_req {
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__u32 reserved32;
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__u8 userspace_ver;
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__u8 reserved8[3];
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};
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struct i40iw_alloc_ucontext_resp {
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__u32 max_pds; /* maximum pds allowed for this user process */
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__u32 max_qps; /* maximum qps allowed for this user process */
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__u32 wq_size; /* size of the WQs (sq+rq) allocated to the mmaped area */
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__u8 kernel_ver;
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__u8 reserved[3];
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};
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struct i40iw_alloc_pd_resp {
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__u32 pd_id;
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__u8 reserved[4];
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};
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struct i40iw_create_cq_req {
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__aligned_u64 user_cq_buffer;
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__aligned_u64 user_shadow_area;
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};
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struct i40iw_create_qp_req {
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__aligned_u64 user_wqe_buffers;
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__aligned_u64 user_compl_ctx;
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/* UDA QP PHB */
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__aligned_u64 user_sq_phb; /* place for VA of the sq phb buff */
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__aligned_u64 user_rq_phb; /* place for VA of the rq phb buff */
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};
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enum i40iw_memreg_type {
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IW_MEMREG_TYPE_MEM = 0x0000,
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IW_MEMREG_TYPE_QP = 0x0001,
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IW_MEMREG_TYPE_CQ = 0x0002,
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};
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struct i40iw_mem_reg_req {
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__u16 reg_type; /* Memory, QP or CQ */
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__u16 cq_pages;
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__u16 rq_pages;
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__u16 sq_pages;
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};
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struct i40iw_create_cq_resp {
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__u32 cq_id;
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__u32 cq_size;
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__u32 mmap_db_index;
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__u32 reserved;
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};
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struct i40iw_create_qp_resp {
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__u32 qp_id;
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__u32 actual_sq_size;
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__u32 actual_rq_size;
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__u32 i40iw_drv_opt;
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__u16 push_idx;
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__u8 lsmm;
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__u8 rsvd2;
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};
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#endif
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