/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2015 Freescale Semiconductor, Inc.
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*/
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#ifndef __LINUX_IMX7_IOMUXC_GPR_H
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#define __LINUX_IMX7_IOMUXC_GPR_H
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#define IOMUXC_GPR0 0x00
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#define IOMUXC_GPR1 0x04
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#define IOMUXC_GPR2 0x08
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#define IOMUXC_GPR3 0x0c
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#define IOMUXC_GPR4 0x10
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#define IOMUXC_GPR5 0x14
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#define IOMUXC_GPR6 0x18
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#define IOMUXC_GPR7 0x1c
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#define IOMUXC_GPR8 0x20
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#define IOMUXC_GPR9 0x24
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#define IOMUXC_GPR10 0x28
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#define IOMUXC_GPR11 0x2c
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#define IOMUXC_GPR12 0x30
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#define IOMUXC_GPR13 0x34
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#define IOMUXC_GPR14 0x38
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#define IOMUXC_GPR15 0x3c
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#define IOMUXC_GPR16 0x40
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#define IOMUXC_GPR17 0x44
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#define IOMUXC_GPR18 0x48
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#define IOMUXC_GPR19 0x4c
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#define IOMUXC_GPR20 0x50
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#define IOMUXC_GPR21 0x54
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#define IOMUXC_GPR22 0x58
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/* For imx7d iomux gpr register field define */
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#define IMX7D_GPR1_IRQ_MASK (0x1 << 12)
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#define IMX7D_GPR1_ENET1_TX_CLK_SEL_MASK (0x1 << 13)
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#define IMX7D_GPR1_ENET2_TX_CLK_SEL_MASK (0x1 << 14)
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#define IMX7D_GPR1_ENET_TX_CLK_SEL_MASK (0x3 << 13)
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#define IMX7D_GPR1_ENET1_CLK_DIR_MASK (0x1 << 17)
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#define IMX7D_GPR1_ENET2_CLK_DIR_MASK (0x1 << 18)
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#define IMX7D_GPR1_ENET_CLK_DIR_MASK (0x3 << 17)
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#define IMX7D_GPR5_CSI_MUX_CONTROL_MIPI (0x1 << 4)
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#define IMX7D_GPR12_PCIE_PHY_REFCLK_SEL BIT(5)
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#define IMX7D_GPR22_PCIE_PHY_PLL_LOCKED BIT(31)
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#endif /* __LINUX_IMX7_IOMUXC_GPR_H */
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