/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Intel MAX 10 Board Management Controller chip.
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*
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* Copyright (C) 2018-2020 Intel Corporation, Inc.
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*/
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#ifndef __MFD_INTEL_M10_BMC_H
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#define __MFD_INTEL_M10_BMC_H
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#include <linux/regmap.h>
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#define M10BMC_LEGACY_SYS_BASE 0x300400
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#define M10BMC_SYS_BASE 0x300800
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#define M10BMC_MEM_END 0x1fffffff
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/* Register offset of system registers */
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#define NIOS2_FW_VERSION 0x0
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#define M10BMC_TEST_REG 0x3c
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#define M10BMC_BUILD_VER 0x68
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#define M10BMC_VER_MAJOR_MSK GENMASK(23, 16)
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#define M10BMC_VER_PCB_INFO_MSK GENMASK(31, 24)
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#define M10BMC_VER_LEGACY_INVALID 0xffffffff
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/**
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* struct intel_m10bmc - Intel MAX 10 BMC parent driver data structure
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* @dev: this device
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* @regmap: the regmap used to access registers by m10bmc itself
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*/
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struct intel_m10bmc {
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struct device *dev;
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struct regmap *regmap;
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};
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/*
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* register access helper functions.
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*
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* m10bmc_raw_read - read m10bmc register per addr
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* m10bmc_sys_read - read m10bmc system register per offset
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*/
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static inline int
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m10bmc_raw_read(struct intel_m10bmc *m10bmc, unsigned int addr,
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unsigned int *val)
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{
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int ret;
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ret = regmap_read(m10bmc->regmap, addr, val);
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if (ret)
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dev_err(m10bmc->dev, "fail to read raw reg %x: %d\n",
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addr, ret);
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return ret;
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}
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/*
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* The base of the system registers could be configured by HW developers, and
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* in HW SPEC, the base is not added to the addresses of the system registers.
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*
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* This macro helps to simplify the accessing of the system registers. And if
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* the base is reconfigured in HW, SW developers could simply change the
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* M10BMC_SYS_BASE accordingly.
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*/
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#define m10bmc_sys_read(m10bmc, offset, val) \
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m10bmc_raw_read(m10bmc, M10BMC_SYS_BASE + (offset), val)
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#endif /* __MFD_INTEL_M10_BMC_H */
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