// SPDX-License-Identifier: GPL-2.0
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#ifndef __FSL_FTM_H__
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#define __FSL_FTM_H__
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#define FTM_SC 0x0 /* Status And Control */
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#define FTM_CNT 0x4 /* Counter */
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#define FTM_MOD 0x8 /* Modulo */
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#define FTM_CNTIN 0x4C /* Counter Initial Value */
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#define FTM_STATUS 0x50 /* Capture And Compare Status */
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#define FTM_MODE 0x54 /* Features Mode Selection */
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#define FTM_SYNC 0x58 /* Synchronization */
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#define FTM_OUTINIT 0x5C /* Initial State For Channels Output */
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#define FTM_OUTMASK 0x60 /* Output Mask */
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#define FTM_COMBINE 0x64 /* Function For Linked Channels */
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#define FTM_DEADTIME 0x68 /* Deadtime Insertion Control */
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#define FTM_EXTTRIG 0x6C /* FTM External Trigger */
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#define FTM_POL 0x70 /* Channels Polarity */
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#define FTM_FMS 0x74 /* Fault Mode Status */
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#define FTM_FILTER 0x78 /* Input Capture Filter Control */
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#define FTM_FLTCTRL 0x7C /* Fault Control */
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#define FTM_QDCTRL 0x80 /* Quadrature Decoder Control And Status */
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#define FTM_CONF 0x84 /* Configuration */
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#define FTM_FLTPOL 0x88 /* FTM Fault Input Polarity */
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#define FTM_SYNCONF 0x8C /* Synchronization Configuration */
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#define FTM_INVCTRL 0x90 /* FTM Inverting Control */
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#define FTM_SWOCTRL 0x94 /* FTM Software Output Control */
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#define FTM_PWMLOAD 0x98 /* FTM PWM Load */
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#define FTM_SC_CLK_MASK_SHIFT 3
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#define FTM_SC_CLK_MASK (3 << FTM_SC_CLK_MASK_SHIFT)
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#define FTM_SC_TOF 0x80
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#define FTM_SC_TOIE 0x40
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#define FTM_SC_CPWMS 0x20
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#define FTM_SC_CLKS 0x18
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#define FTM_SC_PS_1 0x0
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#define FTM_SC_PS_2 0x1
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#define FTM_SC_PS_4 0x2
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#define FTM_SC_PS_8 0x3
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#define FTM_SC_PS_16 0x4
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#define FTM_SC_PS_32 0x5
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#define FTM_SC_PS_64 0x6
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#define FTM_SC_PS_128 0x7
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#define FTM_SC_PS_MASK 0x7
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#define FTM_MODE_FAULTIE 0x80
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#define FTM_MODE_FAULTM 0x60
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#define FTM_MODE_CAPTEST 0x10
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#define FTM_MODE_PWMSYNC 0x8
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#define FTM_MODE_WPDIS 0x4
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#define FTM_MODE_INIT 0x2
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#define FTM_MODE_FTMEN 0x1
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/* NXP Errata: The PHAFLTREN and PHBFLTREN bits are tide to zero internally
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* and these bits cannot be set. Flextimer cannot use Filter in
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* Quadrature Decoder Mode.
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* https://community.nxp.com/thread/467648#comment-1010319
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*/
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#define FTM_QDCTRL_PHAFLTREN 0x80
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#define FTM_QDCTRL_PHBFLTREN 0x40
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#define FTM_QDCTRL_PHAPOL 0x20
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#define FTM_QDCTRL_PHBPOL 0x10
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#define FTM_QDCTRL_QUADMODE 0x8
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#define FTM_QDCTRL_QUADDIR 0x4
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#define FTM_QDCTRL_TOFDIR 0x2
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#define FTM_QDCTRL_QUADEN 0x1
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#define FTM_FMS_FAULTF 0x80
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#define FTM_FMS_WPEN 0x40
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#define FTM_FMS_FAULTIN 0x10
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#define FTM_FMS_FAULTF3 0x8
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#define FTM_FMS_FAULTF2 0x4
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#define FTM_FMS_FAULTF1 0x2
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#define FTM_FMS_FAULTF0 0x1
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#define FTM_CSC_BASE 0xC
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#define FTM_CSC_MSB 0x20
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#define FTM_CSC_MSA 0x10
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#define FTM_CSC_ELSB 0x8
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#define FTM_CSC_ELSA 0x4
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#define FTM_CSC(_channel) (FTM_CSC_BASE + ((_channel) * 8))
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#define FTM_CV_BASE 0x10
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#define FTM_CV(_channel) (FTM_CV_BASE + ((_channel) * 8))
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#define FTM_PS_MAX 7
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#endif
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