/*
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* Copyright (C) 2011 Freescale Semiconductor, Inc.
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* (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef __DW_HDMI__
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#define __DW_HDMI__
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struct dw_hdmi;
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struct drm_display_mode;
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struct ddc_adapter;
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struct i2c_msg;
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/**
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* DOC: Supported input formats and encodings
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*
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* Depending on the Hardware configuration of the Controller IP, it supports
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* a subset of the following input formats and encodings on its internal
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* 48bit bus.
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*
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* +----------------------+----------------------------------+------------------------------+
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* + Format Name + Format Code + Encodings +
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* +----------------------+----------------------------------+------------------------------+
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* + RGB 4:4:4 8bit + ``MEDIA_BUS_FMT_RGB888_1X24`` + ``V4L2_YCBCR_ENC_DEFAULT`` +
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* +----------------------+----------------------------------+------------------------------+
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* + RGB 4:4:4 10bits + ``MEDIA_BUS_FMT_RGB101010_1X30`` + ``V4L2_YCBCR_ENC_DEFAULT`` +
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* +----------------------+----------------------------------+------------------------------+
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* + RGB 4:4:4 12bits + ``MEDIA_BUS_FMT_RGB121212_1X36`` + ``V4L2_YCBCR_ENC_DEFAULT`` +
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* +----------------------+----------------------------------+------------------------------+
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* + RGB 4:4:4 16bits + ``MEDIA_BUS_FMT_RGB161616_1X48`` + ``V4L2_YCBCR_ENC_DEFAULT`` +
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* +----------------------+----------------------------------+------------------------------+
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* + YCbCr 4:4:4 8bit + ``MEDIA_BUS_FMT_YUV8_1X24`` + ``V4L2_YCBCR_ENC_601`` +
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* + + + or ``V4L2_YCBCR_ENC_709`` +
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* + + + or ``V4L2_YCBCR_ENC_XV601`` +
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* + + + or ``V4L2_YCBCR_ENC_XV709`` +
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* +----------------------+----------------------------------+------------------------------+
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* + YCbCr 4:4:4 10bits + ``MEDIA_BUS_FMT_YUV10_1X30`` + ``V4L2_YCBCR_ENC_601`` +
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* + + + or ``V4L2_YCBCR_ENC_709`` +
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* + + + or ``V4L2_YCBCR_ENC_XV601`` +
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* + + + or ``V4L2_YCBCR_ENC_XV709`` +
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* +----------------------+----------------------------------+------------------------------+
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* + YCbCr 4:4:4 12bits + ``MEDIA_BUS_FMT_YUV12_1X36`` + ``V4L2_YCBCR_ENC_601`` +
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* + + + or ``V4L2_YCBCR_ENC_709`` +
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* + + + or ``V4L2_YCBCR_ENC_XV601`` +
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* + + + or ``V4L2_YCBCR_ENC_XV709`` +
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* +----------------------+----------------------------------+------------------------------+
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* + YCbCr 4:4:4 16bits + ``MEDIA_BUS_FMT_YUV16_1X48`` + ``V4L2_YCBCR_ENC_601`` +
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* + + + or ``V4L2_YCBCR_ENC_709`` +
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* + + + or ``V4L2_YCBCR_ENC_XV601`` +
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* + + + or ``V4L2_YCBCR_ENC_XV709`` +
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* +----------------------+----------------------------------+------------------------------+
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* + YCbCr 4:2:2 8bit + ``MEDIA_BUS_FMT_UYVY8_1X16`` + ``V4L2_YCBCR_ENC_601`` +
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* + + + or ``V4L2_YCBCR_ENC_709`` +
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* +----------------------+----------------------------------+------------------------------+
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* + YCbCr 4:2:2 10bits + ``MEDIA_BUS_FMT_UYVY10_1X20`` + ``V4L2_YCBCR_ENC_601`` +
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* + + + or ``V4L2_YCBCR_ENC_709`` +
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* +----------------------+----------------------------------+------------------------------+
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* + YCbCr 4:2:2 12bits + ``MEDIA_BUS_FMT_UYVY12_1X24`` + ``V4L2_YCBCR_ENC_601`` +
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* + + + or ``V4L2_YCBCR_ENC_709`` +
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* +----------------------+----------------------------------+------------------------------+
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* + YCbCr 4:2:0 8bit + ``MEDIA_BUS_FMT_UYYVYY8_0_5X24`` + ``V4L2_YCBCR_ENC_601`` +
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* + + + or ``V4L2_YCBCR_ENC_709`` +
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* +----------------------+----------------------------------+------------------------------+
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* + YCbCr 4:2:0 10bits + ``MEDIA_BUS_FMT_UYYVYY10_0_5X30``+ ``V4L2_YCBCR_ENC_601`` +
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* + + + or ``V4L2_YCBCR_ENC_709`` +
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* +----------------------+----------------------------------+------------------------------+
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* + YCbCr 4:2:0 12bits + ``MEDIA_BUS_FMT_UYYVYY12_0_5X36``+ ``V4L2_YCBCR_ENC_601`` +
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* + + + or ``V4L2_YCBCR_ENC_709`` +
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* +----------------------+----------------------------------+------------------------------+
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* + YCbCr 4:2:0 16bits + ``MEDIA_BUS_FMT_UYYVYY16_0_5X48``+ ``V4L2_YCBCR_ENC_601`` +
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* + + + or ``V4L2_YCBCR_ENC_709`` +
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* +----------------------+----------------------------------+------------------------------+
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*/
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enum {
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DW_HDMI_RES_8,
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DW_HDMI_RES_10,
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DW_HDMI_RES_12,
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DW_HDMI_RES_MAX,
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};
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enum dw_hdmi_devtype {
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IMX6Q_HDMI,
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IMX6DL_HDMI,
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RK3228_HDMI,
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RK3288_HDMI,
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RK3328_HDMI,
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RK3366_HDMI,
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RK3368_HDMI,
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RK3399_HDMI,
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RK3528_HDMI,
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RK3568_HDMI,
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};
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struct dw_hdmi_audio_tmds_n {
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unsigned long tmds;
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unsigned int n_32k;
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unsigned int n_44k1;
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unsigned int n_48k;
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};
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enum dw_hdmi_phy_type {
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DW_HDMI_PHY_DWC_HDMI_TX_PHY = 0x00,
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DW_HDMI_PHY_DWC_MHL_PHY_HEAC = 0xb2,
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DW_HDMI_PHY_DWC_MHL_PHY = 0xc2,
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DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC = 0xe2,
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DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY = 0xf2,
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DW_HDMI_PHY_DWC_HDMI20_TX_PHY = 0xf3,
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DW_HDMI_PHY_VENDOR_PHY = 0xfe,
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};
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struct dw_hdmi_mpll_config {
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unsigned long mpixelclock;
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struct {
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u16 cpce;
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u16 gmp;
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} res[DW_HDMI_RES_MAX];
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};
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struct dw_hdmi_curr_ctrl {
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unsigned long mpixelclock;
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u16 curr[DW_HDMI_RES_MAX];
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};
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struct dw_hdmi_phy_config {
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unsigned long mpixelclock;
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u16 sym_ctr; /*clock symbol and transmitter control*/
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u16 term; /*transmission termination value*/
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u16 vlev_ctr; /* voltage level control */
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};
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struct rockchip_connector;
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struct dw_hdmi_phy_ops {
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int (*init)(struct rockchip_connector *conn, struct dw_hdmi *hdmi, void *data);
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void (*disable)(struct rockchip_connector *conn, struct dw_hdmi *hdmi, void *data);
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enum drm_connector_status (*read_hpd)(struct dw_hdmi *hdmi,
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void *data);
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void (*mode_valid)(struct rockchip_connector *conn, struct dw_hdmi *hdmi, void *data);
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};
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struct dw_hdmi_qp_phy_ops {
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int (*init)(struct rockchip_connector *conn, void *hdmi, void *data);
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void (*disable)(struct rockchip_connector *conn, void *hdmi, void *data);
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enum drm_connector_status (*read_hpd)(void *data);
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void (*mode_valid)(void *hdmi, void *data);
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void (*set_pll)(struct rockchip_connector *conn, void *hdmi, void *data);
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};
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struct dw_hdmi_link_config {
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bool dsc_mode;
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bool frl_mode;
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int frl_lanes;
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int rate_per_lane;
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int hcactive;
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bool allm_en;
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u8 pps_payload[128];
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};
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struct dw_hdmi_plat_data {
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enum dw_hdmi_devtype dev_type;
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unsigned long input_bus_format;
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unsigned long input_bus_encoding;
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u32 vop_sel_bit;
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u32 grf_vop_sel_reg;
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/* Vendor PHY support */
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const struct dw_hdmi_phy_ops *phy_ops;
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const struct dw_hdmi_qp_phy_ops *qp_phy_ops;
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const struct dw_hdmi_audio_tmds_n *tmds_n_table;
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const char *phy_name;
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void *phy_data;
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void *hdmi;
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/* Synopsys PHY support */
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const struct dw_hdmi_mpll_config *mpll_cfg;
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const struct dw_hdmi_mpll_config *mpll_cfg_420;
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const struct dw_hdmi_curr_ctrl *cur_ctr;
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struct dw_hdmi_phy_config *phy_config;
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int (*configure_phy)(struct dw_hdmi *hdmi,
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const struct dw_hdmi_plat_data *pdata,
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unsigned long mpixelclock);
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unsigned long (*get_input_bus_format)(void *data);
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unsigned long (*get_output_bus_format)(void *data);
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unsigned long (*get_enc_in_encoding)(void *data);
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unsigned long (*get_enc_out_encoding)(void *data);
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unsigned long (*get_quant_range)(void *data);
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};
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#endif /* __IMX_HDMI_H__ */
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