/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
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/*
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*
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* (C) COPYRIGHT 2022 ARM Limited. All rights reserved.
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*
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* This program is free software and is provided to you under the terms of the
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* GNU General Public License version 2 as published by the Free Software
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* Foundation, and any use by you of this program is subject to the terms
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* of such GNU license.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you can access it online at
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* http://www.gnu.org/licenses/gpl-2.0.html.
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*
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*/
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#ifndef _UAPI_BASE_COMMON_KERNEL_H_
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#define _UAPI_BASE_COMMON_KERNEL_H_
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#include <linux/types.h>
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struct base_mem_handle {
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struct {
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__u64 handle;
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} basep;
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};
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#define BASE_GPU_NUM_TEXTURE_FEATURES_REGISTERS 4
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/* Memory allocation, access/hint flags & mask.
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*
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* See base_mem_alloc_flags.
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*/
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/* IN */
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/* Read access CPU side
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*/
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#define BASE_MEM_PROT_CPU_RD ((base_mem_alloc_flags)1 << 0)
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/* Write access CPU side
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*/
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#define BASE_MEM_PROT_CPU_WR ((base_mem_alloc_flags)1 << 1)
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/* Read access GPU side
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*/
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#define BASE_MEM_PROT_GPU_RD ((base_mem_alloc_flags)1 << 2)
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/* Write access GPU side
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*/
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#define BASE_MEM_PROT_GPU_WR ((base_mem_alloc_flags)1 << 3)
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/* Execute allowed on the GPU side
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*/
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#define BASE_MEM_PROT_GPU_EX ((base_mem_alloc_flags)1 << 4)
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/* Will be permanently mapped in kernel space.
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* Flag is only allowed on allocations originating from kbase.
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*/
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#define BASEP_MEM_PERMANENT_KERNEL_MAPPING ((base_mem_alloc_flags)1 << 5)
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/* The allocation will completely reside within the same 4GB chunk in the GPU
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* virtual space.
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* Since this flag is primarily required only for the TLS memory which will
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* not be used to contain executable code and also not used for Tiler heap,
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* it can't be used along with BASE_MEM_PROT_GPU_EX and TILER_ALIGN_TOP flags.
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*/
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#define BASE_MEM_GPU_VA_SAME_4GB_PAGE ((base_mem_alloc_flags)1 << 6)
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/* Userspace is not allowed to free this memory.
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* Flag is only allowed on allocations originating from kbase.
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*/
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#define BASEP_MEM_NO_USER_FREE ((base_mem_alloc_flags)1 << 7)
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/* Grow backing store on GPU Page Fault
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*/
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#define BASE_MEM_GROW_ON_GPF ((base_mem_alloc_flags)1 << 9)
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/* Page coherence Outer shareable, if available
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*/
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#define BASE_MEM_COHERENT_SYSTEM ((base_mem_alloc_flags)1 << 10)
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/* Page coherence Inner shareable
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*/
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#define BASE_MEM_COHERENT_LOCAL ((base_mem_alloc_flags)1 << 11)
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/* IN/OUT */
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/* Should be cached on the CPU, returned if actually cached
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*/
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#define BASE_MEM_CACHED_CPU ((base_mem_alloc_flags)1 << 12)
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/* IN/OUT */
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/* Must have same VA on both the GPU and the CPU
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*/
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#define BASE_MEM_SAME_VA ((base_mem_alloc_flags)1 << 13)
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/* OUT */
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/* Must call mmap to acquire a GPU address for the allocation
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*/
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#define BASE_MEM_NEED_MMAP ((base_mem_alloc_flags)1 << 14)
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/* IN */
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/* Page coherence Outer shareable, required.
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*/
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#define BASE_MEM_COHERENT_SYSTEM_REQUIRED ((base_mem_alloc_flags)1 << 15)
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/* Protected memory
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*/
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#define BASE_MEM_PROTECTED ((base_mem_alloc_flags)1 << 16)
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/* Not needed physical memory
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*/
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#define BASE_MEM_DONT_NEED ((base_mem_alloc_flags)1 << 17)
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/* Must use shared CPU/GPU zone (SAME_VA zone) but doesn't require the
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* addresses to be the same
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*/
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#define BASE_MEM_IMPORT_SHARED ((base_mem_alloc_flags)1 << 18)
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/* Should be uncached on the GPU, will work only for GPUs using AARCH64 mmu
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* mode. Some components within the GPU might only be able to access memory
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* that is GPU cacheable. Refer to the specific GPU implementation for more
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* details. The 3 shareability flags will be ignored for GPU uncached memory.
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* If used while importing USER_BUFFER type memory, then the import will fail
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* if the memory is not aligned to GPU and CPU cache line width.
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*/
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#define BASE_MEM_UNCACHED_GPU ((base_mem_alloc_flags)1 << 21)
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/*
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* Bits [22:25] for group_id (0~15).
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*
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* base_mem_group_id_set() should be used to pack a memory group ID into a
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* base_mem_alloc_flags value instead of accessing the bits directly.
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* base_mem_group_id_get() should be used to extract the memory group ID from
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* a base_mem_alloc_flags value.
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*/
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#define BASEP_MEM_GROUP_ID_SHIFT 22
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#define BASE_MEM_GROUP_ID_MASK ((base_mem_alloc_flags)0xF << BASEP_MEM_GROUP_ID_SHIFT)
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/* Must do CPU cache maintenance when imported memory is mapped/unmapped
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* on GPU. Currently applicable to dma-buf type only.
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*/
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#define BASE_MEM_IMPORT_SYNC_ON_MAP_UNMAP ((base_mem_alloc_flags)1 << 26)
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/* OUT */
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/* Kernel side cache sync ops required */
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#define BASE_MEM_KERNEL_SYNC ((base_mem_alloc_flags)1 << 28)
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/* Number of bits used as flags for base memory management
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*
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* Must be kept in sync with the base_mem_alloc_flags flags
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*/
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#define BASE_MEM_FLAGS_NR_BITS 30
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/* A mask for all output bits, excluding IN/OUT bits.
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*/
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#define BASE_MEM_FLAGS_OUTPUT_MASK BASE_MEM_NEED_MMAP
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/* A mask for all input bits, including IN/OUT bits.
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*/
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#define BASE_MEM_FLAGS_INPUT_MASK \
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(((1 << BASE_MEM_FLAGS_NR_BITS) - 1) & ~BASE_MEM_FLAGS_OUTPUT_MASK)
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/* Special base mem handles.
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*/
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#define BASEP_MEM_INVALID_HANDLE (0ul)
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#define BASE_MEM_MMU_DUMP_HANDLE (1ul << LOCAL_PAGE_SHIFT)
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#define BASE_MEM_TRACE_BUFFER_HANDLE (2ul << LOCAL_PAGE_SHIFT)
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#define BASE_MEM_MAP_TRACKING_HANDLE (3ul << LOCAL_PAGE_SHIFT)
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#define BASEP_MEM_WRITE_ALLOC_PAGES_HANDLE (4ul << LOCAL_PAGE_SHIFT)
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/* reserved handles ..-47<<PAGE_SHIFT> for future special handles */
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#define BASE_MEM_COOKIE_BASE (64ul << LOCAL_PAGE_SHIFT)
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#define BASE_MEM_FIRST_FREE_ADDRESS ((BITS_PER_LONG << LOCAL_PAGE_SHIFT) + BASE_MEM_COOKIE_BASE)
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/* Flags to pass to ::base_context_init.
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* Flags can be ORed together to enable multiple things.
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*
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* These share the same space as BASEP_CONTEXT_FLAG_*, and so must
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* not collide with them.
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*/
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typedef __u32 base_context_create_flags;
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/* Flags for base context */
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/* No flags set */
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#define BASE_CONTEXT_CREATE_FLAG_NONE ((base_context_create_flags)0)
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/* Base context is embedded in a cctx object (flag used for CINSTR
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* software counter macros)
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*/
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#define BASE_CONTEXT_CCTX_EMBEDDED ((base_context_create_flags)1 << 0)
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/* Base context is a 'System Monitor' context for Hardware counters.
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*
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* One important side effect of this is that job submission is disabled.
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*/
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#define BASE_CONTEXT_SYSTEM_MONITOR_SUBMIT_DISABLED ((base_context_create_flags)1 << 1)
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/* Bit-shift used to encode a memory group ID in base_context_create_flags
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*/
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#define BASEP_CONTEXT_MMU_GROUP_ID_SHIFT (3)
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/* Bitmask used to encode a memory group ID in base_context_create_flags
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*/
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#define BASEP_CONTEXT_MMU_GROUP_ID_MASK \
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((base_context_create_flags)0xF << BASEP_CONTEXT_MMU_GROUP_ID_SHIFT)
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/* Bitpattern describing the base_context_create_flags that can be
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* passed to the kernel
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*/
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#define BASEP_CONTEXT_CREATE_KERNEL_FLAGS \
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(BASE_CONTEXT_SYSTEM_MONITOR_SUBMIT_DISABLED | BASEP_CONTEXT_MMU_GROUP_ID_MASK)
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/* Flags for base tracepoint
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*/
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/* Enable additional tracepoints for latency measurements (TL_ATOM_READY,
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* TL_ATOM_DONE, TL_ATOM_PRIO_CHANGE, TL_ATOM_EVENT_POST)
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*/
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#define BASE_TLSTREAM_ENABLE_LATENCY_TRACEPOINTS (1 << 0)
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/* Indicate that job dumping is enabled. This could affect certain timers
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* to account for the performance impact.
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*/
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#define BASE_TLSTREAM_JOB_DUMPING_ENABLED (1 << 1)
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#endif /* _UAPI_BASE_COMMON_KERNEL_H_ */
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