/*
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* Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef MLX4_QP_H
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#define MLX4_QP_H
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#include <linux/types.h>
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#include <linux/if_ether.h>
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#include <linux/mlx4/device.h>
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#define MLX4_INVALID_LKEY 0x100
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enum mlx4_qp_optpar {
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MLX4_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0,
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MLX4_QP_OPTPAR_RRE = 1 << 1,
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MLX4_QP_OPTPAR_RAE = 1 << 2,
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MLX4_QP_OPTPAR_RWE = 1 << 3,
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MLX4_QP_OPTPAR_PKEY_INDEX = 1 << 4,
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MLX4_QP_OPTPAR_Q_KEY = 1 << 5,
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MLX4_QP_OPTPAR_RNR_TIMEOUT = 1 << 6,
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MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
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MLX4_QP_OPTPAR_SRA_MAX = 1 << 8,
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MLX4_QP_OPTPAR_RRA_MAX = 1 << 9,
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MLX4_QP_OPTPAR_PM_STATE = 1 << 10,
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MLX4_QP_OPTPAR_RETRY_COUNT = 1 << 12,
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MLX4_QP_OPTPAR_RNR_RETRY = 1 << 13,
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MLX4_QP_OPTPAR_ACK_TIMEOUT = 1 << 14,
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MLX4_QP_OPTPAR_SCHED_QUEUE = 1 << 16,
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MLX4_QP_OPTPAR_COUNTER_INDEX = 1 << 20,
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MLX4_QP_OPTPAR_VLAN_STRIPPING = 1 << 21,
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};
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enum mlx4_qp_state {
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MLX4_QP_STATE_RST = 0,
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MLX4_QP_STATE_INIT = 1,
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MLX4_QP_STATE_RTR = 2,
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MLX4_QP_STATE_RTS = 3,
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MLX4_QP_STATE_SQER = 4,
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MLX4_QP_STATE_SQD = 5,
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MLX4_QP_STATE_ERR = 6,
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MLX4_QP_STATE_SQ_DRAINING = 7,
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MLX4_QP_NUM_STATE
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};
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enum {
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MLX4_QP_ST_RC = 0x0,
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MLX4_QP_ST_UC = 0x1,
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MLX4_QP_ST_RD = 0x2,
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MLX4_QP_ST_UD = 0x3,
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MLX4_QP_ST_XRC = 0x6,
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MLX4_QP_ST_MLX = 0x7
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};
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enum {
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MLX4_QP_PM_MIGRATED = 0x3,
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MLX4_QP_PM_ARMED = 0x0,
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MLX4_QP_PM_REARM = 0x1
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};
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enum {
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/* params1 */
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MLX4_QP_BIT_SRE = 1 << 15,
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MLX4_QP_BIT_SWE = 1 << 14,
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MLX4_QP_BIT_SAE = 1 << 13,
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/* params2 */
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MLX4_QP_BIT_RRE = 1 << 15,
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MLX4_QP_BIT_RWE = 1 << 14,
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MLX4_QP_BIT_RAE = 1 << 13,
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MLX4_QP_BIT_FPP = 1 << 3,
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MLX4_QP_BIT_RIC = 1 << 4,
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};
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enum {
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MLX4_RSS_HASH_XOR = 0,
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MLX4_RSS_HASH_TOP = 1,
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MLX4_RSS_UDP_IPV6 = 1 << 0,
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MLX4_RSS_UDP_IPV4 = 1 << 1,
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MLX4_RSS_TCP_IPV6 = 1 << 2,
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MLX4_RSS_IPV6 = 1 << 3,
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MLX4_RSS_TCP_IPV4 = 1 << 4,
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MLX4_RSS_IPV4 = 1 << 5,
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MLX4_RSS_BY_OUTER_HEADERS = 0 << 6,
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MLX4_RSS_BY_INNER_HEADERS = 2 << 6,
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MLX4_RSS_BY_INNER_HEADERS_IPONLY = 3 << 6,
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/* offset of mlx4_rss_context within mlx4_qp_context.pri_path */
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MLX4_RSS_OFFSET_IN_QPC_PRI_PATH = 0x24,
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/* offset of being RSS indirection QP within mlx4_qp_context.flags */
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MLX4_RSS_QPC_FLAG_OFFSET = 13,
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};
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#define MLX4_EN_RSS_KEY_SIZE 40
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struct mlx4_rss_context {
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__be32 base_qpn;
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__be32 default_qpn;
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u16 reserved;
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u8 hash_fn;
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u8 flags;
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__be32 rss_key[MLX4_EN_RSS_KEY_SIZE / sizeof(__be32)];
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__be32 base_qpn_udp;
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};
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struct mlx4_qp_path {
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u8 fl;
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union {
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u8 vlan_control;
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u8 control;
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};
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u8 disable_pkey_check;
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u8 pkey_index;
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u8 counter_index;
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u8 grh_mylmc;
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__be16 rlid;
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u8 ackto;
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u8 mgid_index;
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u8 static_rate;
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u8 hop_limit;
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__be32 tclass_flowlabel;
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u8 rgid[16];
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u8 sched_queue;
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u8 vlan_index;
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u8 feup;
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u8 fvl_rx;
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u8 reserved4[2];
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u8 dmac[ETH_ALEN];
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};
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enum { /* fl */
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MLX4_FL_CV = 1 << 6,
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MLX4_FL_SV = 1 << 5,
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MLX4_FL_ETH_HIDE_CQE_VLAN = 1 << 2,
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MLX4_FL_ETH_SRC_CHECK_MC_LB = 1 << 1,
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MLX4_FL_ETH_SRC_CHECK_UC_LB = 1 << 0,
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};
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enum { /* control */
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MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER = 1 << 7,
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};
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enum { /* vlan_control */
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MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED = 1 << 6,
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MLX4_VLAN_CTRL_ETH_TX_BLOCK_PRIO_TAGGED = 1 << 5, /* 802.1p priority tag */
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MLX4_VLAN_CTRL_ETH_TX_BLOCK_UNTAGGED = 1 << 4,
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MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED = 1 << 2,
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MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED = 1 << 1, /* 802.1p priority tag */
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MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED = 1 << 0
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};
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enum { /* feup */
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MLX4_FEUP_FORCE_ETH_UP = 1 << 6, /* force Eth UP */
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MLX4_FSM_FORCE_ETH_SRC_MAC = 1 << 5, /* force Source MAC */
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MLX4_FVL_FORCE_ETH_VLAN = 1 << 3 /* force Eth vlan */
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};
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enum { /* fvl_rx */
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MLX4_FVL_RX_FORCE_ETH_VLAN = 1 << 0 /* enforce Eth rx vlan */
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};
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struct mlx4_qp_context {
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__be32 flags;
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__be32 pd;
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u8 mtu_msgmax;
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u8 rq_size_stride;
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u8 sq_size_stride;
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u8 rlkey_roce_mode;
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__be32 usr_page;
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__be32 local_qpn;
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__be32 remote_qpn;
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struct mlx4_qp_path pri_path;
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struct mlx4_qp_path alt_path;
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__be32 params1;
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u32 reserved1;
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__be32 next_send_psn;
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__be32 cqn_send;
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__be16 roce_entropy;
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__be16 reserved2[3];
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__be32 last_acked_psn;
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__be32 ssn;
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__be32 params2;
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__be32 rnr_nextrecvpsn;
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__be32 xrcd;
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__be32 cqn_recv;
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__be64 db_rec_addr;
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__be32 qkey;
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__be32 srqn;
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__be32 msn;
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__be16 rq_wqe_counter;
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__be16 sq_wqe_counter;
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u32 reserved3;
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__be16 rate_limit_params;
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u8 reserved4;
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u8 qos_vport;
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__be32 param3;
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__be32 nummmcpeers_basemkey;
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u8 log_page_size;
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u8 reserved5[2];
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u8 mtt_base_addr_h;
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__be32 mtt_base_addr_l;
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u32 reserved6[10];
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};
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struct mlx4_update_qp_context {
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__be64 qp_mask;
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__be64 primary_addr_path_mask;
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__be64 secondary_addr_path_mask;
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u64 reserved1;
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struct mlx4_qp_context qp_context;
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u64 reserved2[58];
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};
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enum {
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MLX4_UPD_QP_MASK_PM_STATE = 32,
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MLX4_UPD_QP_MASK_VSD = 33,
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MLX4_UPD_QP_MASK_QOS_VPP = 34,
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MLX4_UPD_QP_MASK_RATE_LIMIT = 35,
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};
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enum {
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MLX4_UPD_QP_PATH_MASK_PKEY_INDEX = 0 + 32,
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MLX4_UPD_QP_PATH_MASK_FSM = 1 + 32,
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MLX4_UPD_QP_PATH_MASK_MAC_INDEX = 2 + 32,
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MLX4_UPD_QP_PATH_MASK_FVL = 3 + 32,
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MLX4_UPD_QP_PATH_MASK_CV = 4 + 32,
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MLX4_UPD_QP_PATH_MASK_VLAN_INDEX = 5 + 32,
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MLX4_UPD_QP_PATH_MASK_ETH_HIDE_CQE_VLAN = 6 + 32,
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MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_UNTAGGED = 7 + 32,
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MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_1P = 8 + 32,
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MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_TAGGED = 9 + 32,
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MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_UNTAGGED = 10 + 32,
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MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_1P = 11 + 32,
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MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_TAGGED = 12 + 32,
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MLX4_UPD_QP_PATH_MASK_FEUP = 13 + 32,
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MLX4_UPD_QP_PATH_MASK_SCHED_QUEUE = 14 + 32,
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MLX4_UPD_QP_PATH_MASK_IF_COUNTER_INDEX = 15 + 32,
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MLX4_UPD_QP_PATH_MASK_FVL_RX = 16 + 32,
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MLX4_UPD_QP_PATH_MASK_ETH_SRC_CHECK_UC_LB = 18 + 32,
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MLX4_UPD_QP_PATH_MASK_ETH_SRC_CHECK_MC_LB = 19 + 32,
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MLX4_UPD_QP_PATH_MASK_SV = 22 + 32,
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};
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enum { /* param3 */
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MLX4_STRIP_VLAN = 1 << 30
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};
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/* Which firmware version adds support for NEC (NoErrorCompletion) bit */
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#define MLX4_FW_VER_WQE_CTRL_NEC mlx4_fw_ver(2, 2, 232)
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enum {
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MLX4_WQE_CTRL_NEC = 1 << 29,
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MLX4_WQE_CTRL_IIP = 1 << 28,
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MLX4_WQE_CTRL_ILP = 1 << 27,
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MLX4_WQE_CTRL_FENCE = 1 << 6,
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MLX4_WQE_CTRL_CQ_UPDATE = 3 << 2,
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MLX4_WQE_CTRL_SOLICITED = 1 << 1,
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MLX4_WQE_CTRL_IP_CSUM = 1 << 4,
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MLX4_WQE_CTRL_TCP_UDP_CSUM = 1 << 5,
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MLX4_WQE_CTRL_INS_CVLAN = 1 << 6,
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MLX4_WQE_CTRL_INS_SVLAN = 1 << 7,
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MLX4_WQE_CTRL_STRONG_ORDER = 1 << 7,
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MLX4_WQE_CTRL_FORCE_LOOPBACK = 1 << 0,
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};
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union mlx4_wqe_qpn_vlan {
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struct {
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__be16 vlan_tag;
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u8 ins_vlan;
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u8 fence_size;
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};
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__be32 bf_qpn;
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};
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struct mlx4_wqe_ctrl_seg {
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__be32 owner_opcode;
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union mlx4_wqe_qpn_vlan qpn_vlan;
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/*
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* High 24 bits are SRC remote buffer; low 8 bits are flags:
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* [7] SO (strong ordering)
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* [5] TCP/UDP checksum
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* [4] IP checksum
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* [3:2] C (generate completion queue entry)
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* [1] SE (solicited event)
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* [0] FL (force loopback)
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*/
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union {
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__be32 srcrb_flags;
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__be16 srcrb_flags16[2];
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};
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/*
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* imm is immediate data for send/RDMA write w/ immediate;
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* also invalidation key for send with invalidate; input
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* modifier for WQEs on CCQs.
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*/
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__be32 imm;
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};
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enum {
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MLX4_WQE_MLX_VL15 = 1 << 17,
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MLX4_WQE_MLX_SLR = 1 << 16
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};
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struct mlx4_wqe_mlx_seg {
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u8 owner;
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u8 reserved1[2];
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u8 opcode;
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__be16 sched_prio;
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u8 reserved2;
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u8 size;
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/*
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* [17] VL15
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* [16] SLR
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* [15:12] static rate
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* [11:8] SL
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* [4] ICRC
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* [3:2] C
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* [0] FL (force loopback)
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*/
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__be32 flags;
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__be16 rlid;
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u16 reserved3;
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};
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struct mlx4_wqe_datagram_seg {
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__be32 av[8];
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__be32 dqpn;
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__be32 qkey;
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__be16 vlan;
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u8 mac[ETH_ALEN];
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};
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struct mlx4_wqe_lso_seg {
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__be32 mss_hdr_size;
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__be32 header[];
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};
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enum mlx4_wqe_bind_seg_flags2 {
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MLX4_WQE_BIND_ZERO_BASED = (1 << 30),
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MLX4_WQE_BIND_TYPE_2 = (1 << 31),
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};
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struct mlx4_wqe_bind_seg {
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__be32 flags1;
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__be32 flags2;
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__be32 new_rkey;
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__be32 lkey;
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__be64 addr;
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__be64 length;
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};
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enum {
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MLX4_WQE_FMR_PERM_LOCAL_READ = 1 << 27,
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MLX4_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28,
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MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ = 1 << 29,
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MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE = 1 << 30,
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MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC = 1 << 31
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};
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struct mlx4_wqe_fmr_seg {
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__be32 flags;
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__be32 mem_key;
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__be64 buf_list;
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__be64 start_addr;
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__be64 reg_len;
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__be32 offset;
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__be32 page_size;
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u32 reserved[2];
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};
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struct mlx4_wqe_fmr_ext_seg {
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u8 flags;
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u8 reserved;
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__be16 app_mask;
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__be16 wire_app_tag;
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__be16 mem_app_tag;
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__be32 wire_ref_tag_base;
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__be32 mem_ref_tag_base;
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};
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struct mlx4_wqe_local_inval_seg {
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u64 reserved1;
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__be32 mem_key;
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u32 reserved2;
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u64 reserved3[2];
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};
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struct mlx4_wqe_raddr_seg {
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__be64 raddr;
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__be32 rkey;
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u32 reserved;
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};
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struct mlx4_wqe_atomic_seg {
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__be64 swap_add;
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__be64 compare;
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};
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struct mlx4_wqe_masked_atomic_seg {
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__be64 swap_add;
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__be64 compare;
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__be64 swap_add_mask;
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__be64 compare_mask;
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};
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struct mlx4_wqe_data_seg {
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__be32 byte_count;
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__be32 lkey;
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__be64 addr;
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};
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enum {
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MLX4_INLINE_ALIGN = 64,
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MLX4_INLINE_SEG = 1 << 31,
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};
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struct mlx4_wqe_inline_seg {
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__be32 byte_count;
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};
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enum mlx4_update_qp_attr {
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MLX4_UPDATE_QP_SMAC = 1 << 0,
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MLX4_UPDATE_QP_VSD = 1 << 1,
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MLX4_UPDATE_QP_RATE_LIMIT = 1 << 2,
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MLX4_UPDATE_QP_QOS_VPORT = 1 << 3,
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MLX4_UPDATE_QP_ETH_SRC_CHECK_MC_LB = 1 << 4,
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MLX4_UPDATE_QP_SUPPORTED_ATTRS = (1 << 5) - 1
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};
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enum mlx4_update_qp_params_flags {
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MLX4_UPDATE_QP_PARAMS_FLAGS_ETH_CHECK_MC_LB = 1 << 0,
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MLX4_UPDATE_QP_PARAMS_FLAGS_VSD_ENABLE = 1 << 1,
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};
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struct mlx4_update_qp_params {
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u8 smac_index;
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u8 qos_vport;
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u32 flags;
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u16 rate_unit;
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u16 rate_val;
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};
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struct mlx4_qp *mlx4_qp_lookup(struct mlx4_dev *dev, u32 qpn);
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int mlx4_update_qp(struct mlx4_dev *dev, u32 qpn,
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enum mlx4_update_qp_attr attr,
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struct mlx4_update_qp_params *params);
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int mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
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enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state,
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struct mlx4_qp_context *context, enum mlx4_qp_optpar optpar,
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int sqd_event, struct mlx4_qp *qp);
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int mlx4_qp_query(struct mlx4_dev *dev, struct mlx4_qp *qp,
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struct mlx4_qp_context *context);
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int mlx4_qp_to_ready(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
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struct mlx4_qp_context *context,
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struct mlx4_qp *qp, enum mlx4_qp_state *qp_state);
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static inline struct mlx4_qp *__mlx4_qp_lookup(struct mlx4_dev *dev, u32 qpn)
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{
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return radix_tree_lookup(&dev->qp_table_tree, qpn & (dev->caps.num_qps - 1));
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}
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void mlx4_qp_remove(struct mlx4_dev *dev, struct mlx4_qp *qp);
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static inline u16 folded_qp(u32 q)
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{
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u16 res;
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res = ((q & 0xff) ^ ((q & 0xff0000) >> 16)) | (q & 0xff00);
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return res;
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}
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u16 mlx4_qp_roce_entropy(struct mlx4_dev *dev, u32 qpn);
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#endif /* MLX4_QP_H */
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