// SPDX-License-Identifier: GPL-2.0-only
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/*
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* This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
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* DWC Ether MAC version 4.00 has been used for developing this code.
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*
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* This only implements the mac core functions for this chip.
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*
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* Copyright (C) 2015 STMicroelectronics Ltd
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*
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* Author: Alexandre Torgue <alexandre.torgue@st.com>
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*/
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#include <linux/crc32.h>
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#include <linux/slab.h>
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#include <linux/ethtool.h>
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#include <linux/io.h>
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#include <net/dsa.h>
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#include "stmmac.h"
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#include "stmmac_pcs.h"
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#include "dwmac4.h"
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#include "dwmac5.h"
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static void dwmac4_core_init(struct mac_device_info *hw,
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struct net_device *dev)
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{
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void __iomem *ioaddr = hw->pcsr;
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u32 value = readl(ioaddr + GMAC_CONFIG);
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value |= GMAC_CORE_INIT;
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if (hw->ps) {
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value |= GMAC_CONFIG_TE;
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value &= hw->link.speed_mask;
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switch (hw->ps) {
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case SPEED_1000:
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value |= hw->link.speed1000;
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break;
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case SPEED_100:
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value |= hw->link.speed100;
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break;
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case SPEED_10:
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value |= hw->link.speed10;
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break;
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}
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}
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writel(value, ioaddr + GMAC_CONFIG);
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/* Enable GMAC interrupts */
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value = GMAC_INT_DEFAULT_ENABLE;
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if (hw->pcs)
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value |= GMAC_PCS_IRQ_DEFAULT;
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writel(value, ioaddr + GMAC_INT_EN);
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}
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static void dwmac4_rx_queue_enable(struct mac_device_info *hw,
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u8 mode, u32 queue)
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{
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void __iomem *ioaddr = hw->pcsr;
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u32 value = readl(ioaddr + GMAC_RXQ_CTRL0);
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value &= GMAC_RX_QUEUE_CLEAR(queue);
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if (mode == MTL_QUEUE_AVB)
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value |= GMAC_RX_AV_QUEUE_ENABLE(queue);
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else if (mode == MTL_QUEUE_DCB)
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value |= GMAC_RX_DCB_QUEUE_ENABLE(queue);
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writel(value, ioaddr + GMAC_RXQ_CTRL0);
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}
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static void dwmac4_rx_queue_priority(struct mac_device_info *hw,
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u32 prio, u32 queue)
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{
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void __iomem *ioaddr = hw->pcsr;
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u32 base_register;
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u32 value;
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base_register = (queue < 4) ? GMAC_RXQ_CTRL2 : GMAC_RXQ_CTRL3;
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if (queue >= 4)
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queue -= 4;
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value = readl(ioaddr + base_register);
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value &= ~GMAC_RXQCTRL_PSRQX_MASK(queue);
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value |= (prio << GMAC_RXQCTRL_PSRQX_SHIFT(queue)) &
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GMAC_RXQCTRL_PSRQX_MASK(queue);
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writel(value, ioaddr + base_register);
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}
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static void dwmac4_tx_queue_priority(struct mac_device_info *hw,
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u32 prio, u32 queue)
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{
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void __iomem *ioaddr = hw->pcsr;
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u32 base_register;
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u32 value;
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base_register = (queue < 4) ? GMAC_TXQ_PRTY_MAP0 : GMAC_TXQ_PRTY_MAP1;
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if (queue >= 4)
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queue -= 4;
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value = readl(ioaddr + base_register);
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value &= ~GMAC_TXQCTRL_PSTQX_MASK(queue);
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value |= (prio << GMAC_TXQCTRL_PSTQX_SHIFT(queue)) &
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GMAC_TXQCTRL_PSTQX_MASK(queue);
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writel(value, ioaddr + base_register);
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}
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static void dwmac4_rx_queue_routing(struct mac_device_info *hw,
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u8 packet, u32 queue)
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{
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void __iomem *ioaddr = hw->pcsr;
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u32 value;
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static const struct stmmac_rx_routing route_possibilities[] = {
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{ GMAC_RXQCTRL_AVCPQ_MASK, GMAC_RXQCTRL_AVCPQ_SHIFT },
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{ GMAC_RXQCTRL_PTPQ_MASK, GMAC_RXQCTRL_PTPQ_SHIFT },
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{ GMAC_RXQCTRL_DCBCPQ_MASK, GMAC_RXQCTRL_DCBCPQ_SHIFT },
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{ GMAC_RXQCTRL_UPQ_MASK, GMAC_RXQCTRL_UPQ_SHIFT },
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{ GMAC_RXQCTRL_MCBCQ_MASK, GMAC_RXQCTRL_MCBCQ_SHIFT },
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};
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value = readl(ioaddr + GMAC_RXQ_CTRL1);
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/* routing configuration */
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value &= ~route_possibilities[packet - 1].reg_mask;
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value |= (queue << route_possibilities[packet-1].reg_shift) &
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route_possibilities[packet - 1].reg_mask;
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/* some packets require extra ops */
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if (packet == PACKET_AVCPQ) {
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value &= ~GMAC_RXQCTRL_TACPQE;
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value |= 0x1 << GMAC_RXQCTRL_TACPQE_SHIFT;
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} else if (packet == PACKET_MCBCQ) {
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value &= ~GMAC_RXQCTRL_MCBCQEN;
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value |= 0x1 << GMAC_RXQCTRL_MCBCQEN_SHIFT;
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}
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writel(value, ioaddr + GMAC_RXQ_CTRL1);
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}
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static void dwmac4_prog_mtl_rx_algorithms(struct mac_device_info *hw,
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u32 rx_alg)
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{
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void __iomem *ioaddr = hw->pcsr;
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u32 value = readl(ioaddr + MTL_OPERATION_MODE);
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value &= ~MTL_OPERATION_RAA;
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switch (rx_alg) {
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case MTL_RX_ALGORITHM_SP:
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value |= MTL_OPERATION_RAA_SP;
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break;
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case MTL_RX_ALGORITHM_WSP:
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value |= MTL_OPERATION_RAA_WSP;
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break;
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default:
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break;
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}
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writel(value, ioaddr + MTL_OPERATION_MODE);
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}
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static void dwmac4_prog_mtl_tx_algorithms(struct mac_device_info *hw,
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u32 tx_alg)
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{
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void __iomem *ioaddr = hw->pcsr;
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u32 value = readl(ioaddr + MTL_OPERATION_MODE);
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value &= ~MTL_OPERATION_SCHALG_MASK;
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switch (tx_alg) {
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case MTL_TX_ALGORITHM_WRR:
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value |= MTL_OPERATION_SCHALG_WRR;
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break;
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case MTL_TX_ALGORITHM_WFQ:
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value |= MTL_OPERATION_SCHALG_WFQ;
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break;
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case MTL_TX_ALGORITHM_DWRR:
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value |= MTL_OPERATION_SCHALG_DWRR;
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break;
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case MTL_TX_ALGORITHM_SP:
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value |= MTL_OPERATION_SCHALG_SP;
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break;
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default:
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break;
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}
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writel(value, ioaddr + MTL_OPERATION_MODE);
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}
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static void dwmac4_set_mtl_tx_queue_weight(struct mac_device_info *hw,
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u32 weight, u32 queue)
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{
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void __iomem *ioaddr = hw->pcsr;
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u32 value = readl(ioaddr + MTL_TXQX_WEIGHT_BASE_ADDR(queue));
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value &= ~MTL_TXQ_WEIGHT_ISCQW_MASK;
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value |= weight & MTL_TXQ_WEIGHT_ISCQW_MASK;
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writel(value, ioaddr + MTL_TXQX_WEIGHT_BASE_ADDR(queue));
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}
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static void dwmac4_map_mtl_dma(struct mac_device_info *hw, u32 queue, u32 chan)
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{
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void __iomem *ioaddr = hw->pcsr;
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u32 value;
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if (queue < 4)
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value = readl(ioaddr + MTL_RXQ_DMA_MAP0);
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else
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value = readl(ioaddr + MTL_RXQ_DMA_MAP1);
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if (queue == 0 || queue == 4) {
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value &= ~MTL_RXQ_DMA_Q04MDMACH_MASK;
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value |= MTL_RXQ_DMA_Q04MDMACH(chan);
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} else if (queue > 4) {
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value &= ~MTL_RXQ_DMA_QXMDMACH_MASK(queue - 4);
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value |= MTL_RXQ_DMA_QXMDMACH(chan, queue - 4);
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} else {
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value &= ~MTL_RXQ_DMA_QXMDMACH_MASK(queue);
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value |= MTL_RXQ_DMA_QXMDMACH(chan, queue);
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}
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if (queue < 4)
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writel(value, ioaddr + MTL_RXQ_DMA_MAP0);
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else
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writel(value, ioaddr + MTL_RXQ_DMA_MAP1);
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}
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static void dwmac4_config_cbs(struct mac_device_info *hw,
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u32 send_slope, u32 idle_slope,
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u32 high_credit, u32 low_credit, u32 queue)
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{
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void __iomem *ioaddr = hw->pcsr;
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u32 value;
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pr_debug("Queue %d configured as AVB. Parameters:\n", queue);
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pr_debug("\tsend_slope: 0x%08x\n", send_slope);
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pr_debug("\tidle_slope: 0x%08x\n", idle_slope);
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pr_debug("\thigh_credit: 0x%08x\n", high_credit);
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pr_debug("\tlow_credit: 0x%08x\n", low_credit);
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/* enable AV algorithm */
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value = readl(ioaddr + MTL_ETSX_CTRL_BASE_ADDR(queue));
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value |= MTL_ETS_CTRL_AVALG;
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value |= MTL_ETS_CTRL_CC;
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writel(value, ioaddr + MTL_ETSX_CTRL_BASE_ADDR(queue));
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/* configure send slope */
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value = readl(ioaddr + MTL_SEND_SLP_CREDX_BASE_ADDR(queue));
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value &= ~MTL_SEND_SLP_CRED_SSC_MASK;
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value |= send_slope & MTL_SEND_SLP_CRED_SSC_MASK;
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writel(value, ioaddr + MTL_SEND_SLP_CREDX_BASE_ADDR(queue));
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/* configure idle slope (same register as tx weight) */
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dwmac4_set_mtl_tx_queue_weight(hw, idle_slope, queue);
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/* configure high credit */
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value = readl(ioaddr + MTL_HIGH_CREDX_BASE_ADDR(queue));
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value &= ~MTL_HIGH_CRED_HC_MASK;
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value |= high_credit & MTL_HIGH_CRED_HC_MASK;
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writel(value, ioaddr + MTL_HIGH_CREDX_BASE_ADDR(queue));
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/* configure high credit */
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value = readl(ioaddr + MTL_LOW_CREDX_BASE_ADDR(queue));
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value &= ~MTL_HIGH_CRED_LC_MASK;
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value |= low_credit & MTL_HIGH_CRED_LC_MASK;
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writel(value, ioaddr + MTL_LOW_CREDX_BASE_ADDR(queue));
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}
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static void dwmac4_dump_regs(struct mac_device_info *hw, u32 *reg_space)
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{
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void __iomem *ioaddr = hw->pcsr;
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int i;
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for (i = 0; i < GMAC_REG_NUM; i++)
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reg_space[i] = readl(ioaddr + i * 4);
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}
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static int dwmac4_rx_ipc_enable(struct mac_device_info *hw)
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{
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void __iomem *ioaddr = hw->pcsr;
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u32 value = readl(ioaddr + GMAC_CONFIG);
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if (hw->rx_csum)
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value |= GMAC_CONFIG_IPC;
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else
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value &= ~GMAC_CONFIG_IPC;
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writel(value, ioaddr + GMAC_CONFIG);
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value = readl(ioaddr + GMAC_CONFIG);
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return !!(value & GMAC_CONFIG_IPC);
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}
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static void dwmac4_pmt(struct mac_device_info *hw, unsigned long mode)
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{
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void __iomem *ioaddr = hw->pcsr;
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unsigned int pmt = 0;
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u32 config;
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if (mode & WAKE_MAGIC) {
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pr_debug("GMAC: WOL Magic frame\n");
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pmt |= power_down | magic_pkt_en;
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}
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if (mode & WAKE_UCAST) {
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pr_debug("GMAC: WOL on global unicast\n");
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pmt |= power_down | global_unicast | wake_up_frame_en;
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}
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if (pmt) {
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/* The receiver must be enabled for WOL before powering down */
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config = readl(ioaddr + GMAC_CONFIG);
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config |= GMAC_CONFIG_RE;
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writel(config, ioaddr + GMAC_CONFIG);
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}
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writel(pmt, ioaddr + GMAC_PMT);
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}
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static void dwmac4_set_umac_addr(struct mac_device_info *hw,
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unsigned char *addr, unsigned int reg_n)
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{
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void __iomem *ioaddr = hw->pcsr;
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stmmac_dwmac4_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
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GMAC_ADDR_LOW(reg_n));
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}
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static void dwmac4_get_umac_addr(struct mac_device_info *hw,
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unsigned char *addr, unsigned int reg_n)
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{
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void __iomem *ioaddr = hw->pcsr;
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stmmac_dwmac4_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
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GMAC_ADDR_LOW(reg_n));
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}
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static void dwmac4_set_eee_mode(struct mac_device_info *hw,
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bool en_tx_lpi_clockgating)
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{
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void __iomem *ioaddr = hw->pcsr;
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u32 value;
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/* Enable the link status receive on RGMII, SGMII ore SMII
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* receive path and instruct the transmit to enter in LPI
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* state.
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*/
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value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
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value |= GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA;
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if (en_tx_lpi_clockgating)
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value |= GMAC4_LPI_CTRL_STATUS_LPITCSE;
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writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
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}
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static void dwmac4_reset_eee_mode(struct mac_device_info *hw)
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{
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void __iomem *ioaddr = hw->pcsr;
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u32 value;
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value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
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value &= ~(GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA);
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writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
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}
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static void dwmac4_set_eee_pls(struct mac_device_info *hw, int link)
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{
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void __iomem *ioaddr = hw->pcsr;
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u32 value;
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value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
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if (link)
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value |= GMAC4_LPI_CTRL_STATUS_PLS;
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else
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value &= ~GMAC4_LPI_CTRL_STATUS_PLS;
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writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
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}
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static void dwmac4_set_eee_timer(struct mac_device_info *hw, int ls, int tw)
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{
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void __iomem *ioaddr = hw->pcsr;
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int value = ((tw & 0xffff)) | ((ls & 0x3ff) << 16);
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/* Program the timers in the LPI timer control register:
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* LS: minimum time (ms) for which the link
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* status from PHY should be ok before transmitting
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* the LPI pattern.
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* TW: minimum time (us) for which the core waits
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* after it has stopped transmitting the LPI pattern.
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*/
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writel(value, ioaddr + GMAC4_LPI_TIMER_CTRL);
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}
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static void dwmac4_write_single_vlan(struct net_device *dev, u16 vid)
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{
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void __iomem *ioaddr = (void __iomem *)dev->base_addr;
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u32 val;
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val = readl(ioaddr + GMAC_VLAN_TAG);
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val &= ~GMAC_VLAN_TAG_VID;
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val |= GMAC_VLAN_TAG_ETV | vid;
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writel(val, ioaddr + GMAC_VLAN_TAG);
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}
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static int dwmac4_write_vlan_filter(struct net_device *dev,
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struct mac_device_info *hw,
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u8 index, u32 data)
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{
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void __iomem *ioaddr = (void __iomem *)dev->base_addr;
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int i, timeout = 10;
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u32 val;
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if (index >= hw->num_vlan)
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return -EINVAL;
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writel(data, ioaddr + GMAC_VLAN_TAG_DATA);
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val = readl(ioaddr + GMAC_VLAN_TAG);
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val &= ~(GMAC_VLAN_TAG_CTRL_OFS_MASK |
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GMAC_VLAN_TAG_CTRL_CT |
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GMAC_VLAN_TAG_CTRL_OB);
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val |= (index << GMAC_VLAN_TAG_CTRL_OFS_SHIFT) | GMAC_VLAN_TAG_CTRL_OB;
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writel(val, ioaddr + GMAC_VLAN_TAG);
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for (i = 0; i < timeout; i++) {
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val = readl(ioaddr + GMAC_VLAN_TAG);
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if (!(val & GMAC_VLAN_TAG_CTRL_OB))
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return 0;
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udelay(1);
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}
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netdev_err(dev, "Timeout accessing MAC_VLAN_Tag_Filter\n");
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return -EBUSY;
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}
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static int dwmac4_add_hw_vlan_rx_fltr(struct net_device *dev,
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struct mac_device_info *hw,
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__be16 proto, u16 vid)
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{
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int index = -1;
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u32 val = 0;
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int i, ret;
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if (vid > 4095)
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return -EINVAL;
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/* Single Rx VLAN Filter */
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if (hw->num_vlan == 1) {
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/* For single VLAN filter, VID 0 means VLAN promiscuous */
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if (vid == 0) {
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netdev_warn(dev, "Adding VLAN ID 0 is not supported\n");
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return -EPERM;
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}
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if (hw->vlan_filter[0] & GMAC_VLAN_TAG_VID) {
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netdev_err(dev, "Only single VLAN ID supported\n");
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return -EPERM;
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}
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hw->vlan_filter[0] = vid;
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dwmac4_write_single_vlan(dev, vid);
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return 0;
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}
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/* Extended Rx VLAN Filter Enable */
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val |= GMAC_VLAN_TAG_DATA_ETV | GMAC_VLAN_TAG_DATA_VEN | vid;
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for (i = 0; i < hw->num_vlan; i++) {
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if (hw->vlan_filter[i] == val)
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return 0;
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else if (!(hw->vlan_filter[i] & GMAC_VLAN_TAG_DATA_VEN))
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index = i;
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}
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if (index == -1) {
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netdev_err(dev, "MAC_VLAN_Tag_Filter full (size: %0u)\n",
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hw->num_vlan);
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return -EPERM;
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}
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ret = dwmac4_write_vlan_filter(dev, hw, index, val);
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if (!ret)
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hw->vlan_filter[index] = val;
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return ret;
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}
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static int dwmac4_del_hw_vlan_rx_fltr(struct net_device *dev,
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struct mac_device_info *hw,
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__be16 proto, u16 vid)
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{
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int i, ret = 0;
|
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/* Single Rx VLAN Filter */
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if (hw->num_vlan == 1) {
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if ((hw->vlan_filter[0] & GMAC_VLAN_TAG_VID) == vid) {
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hw->vlan_filter[0] = 0;
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dwmac4_write_single_vlan(dev, 0);
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}
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return 0;
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}
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/* Extended Rx VLAN Filter Enable */
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for (i = 0; i < hw->num_vlan; i++) {
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if ((hw->vlan_filter[i] & GMAC_VLAN_TAG_DATA_VID) == vid) {
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ret = dwmac4_write_vlan_filter(dev, hw, i, 0);
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if (!ret)
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hw->vlan_filter[i] = 0;
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else
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return ret;
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}
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}
|
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return ret;
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}
|
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static void dwmac4_vlan_promisc_enable(struct net_device *dev,
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struct mac_device_info *hw)
|
{
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void __iomem *ioaddr = hw->pcsr;
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u32 value;
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u32 hash;
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u32 val;
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int i;
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/* Single Rx VLAN Filter */
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if (hw->num_vlan == 1) {
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dwmac4_write_single_vlan(dev, 0);
|
return;
|
}
|
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/* Extended Rx VLAN Filter Enable */
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for (i = 0; i < hw->num_vlan; i++) {
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if (hw->vlan_filter[i] & GMAC_VLAN_TAG_DATA_VEN) {
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val = hw->vlan_filter[i] & ~GMAC_VLAN_TAG_DATA_VEN;
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dwmac4_write_vlan_filter(dev, hw, i, val);
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}
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}
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hash = readl(ioaddr + GMAC_VLAN_HASH_TABLE);
|
if (hash & GMAC_VLAN_VLHT) {
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value = readl(ioaddr + GMAC_VLAN_TAG);
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if (value & GMAC_VLAN_VTHM) {
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value &= ~GMAC_VLAN_VTHM;
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writel(value, ioaddr + GMAC_VLAN_TAG);
|
}
|
}
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}
|
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static void dwmac4_restore_hw_vlan_rx_fltr(struct net_device *dev,
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struct mac_device_info *hw)
|
{
|
void __iomem *ioaddr = hw->pcsr;
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u32 value;
|
u32 hash;
|
u32 val;
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int i;
|
|
/* Single Rx VLAN Filter */
|
if (hw->num_vlan == 1) {
|
dwmac4_write_single_vlan(dev, hw->vlan_filter[0]);
|
return;
|
}
|
|
/* Extended Rx VLAN Filter Enable */
|
for (i = 0; i < hw->num_vlan; i++) {
|
if (hw->vlan_filter[i] & GMAC_VLAN_TAG_DATA_VEN) {
|
val = hw->vlan_filter[i];
|
dwmac4_write_vlan_filter(dev, hw, i, val);
|
}
|
}
|
|
hash = readl(ioaddr + GMAC_VLAN_HASH_TABLE);
|
if (hash & GMAC_VLAN_VLHT) {
|
value = readl(ioaddr + GMAC_VLAN_TAG);
|
value |= GMAC_VLAN_VTHM;
|
writel(value, ioaddr + GMAC_VLAN_TAG);
|
}
|
}
|
|
static void dwmac4_set_filter(struct mac_device_info *hw,
|
struct net_device *dev)
|
{
|
void __iomem *ioaddr = (void __iomem *)dev->base_addr;
|
int numhashregs = (hw->multicast_filter_bins >> 5);
|
int mcbitslog2 = hw->mcast_bits_log2;
|
unsigned int value;
|
u32 mc_filter[8];
|
int i;
|
|
memset(mc_filter, 0, sizeof(mc_filter));
|
|
value = readl(ioaddr + GMAC_PACKET_FILTER);
|
value &= ~GMAC_PACKET_FILTER_HMC;
|
value &= ~GMAC_PACKET_FILTER_HPF;
|
value &= ~GMAC_PACKET_FILTER_PCF;
|
value &= ~GMAC_PACKET_FILTER_PM;
|
value &= ~GMAC_PACKET_FILTER_PR;
|
value &= ~GMAC_PACKET_FILTER_RA;
|
if (dev->flags & IFF_PROMISC) {
|
/* VLAN Tag Filter Fail Packets Queuing */
|
if (hw->vlan_fail_q_en) {
|
value = readl(ioaddr + GMAC_RXQ_CTRL4);
|
value &= ~GMAC_RXQCTRL_VFFQ_MASK;
|
value |= GMAC_RXQCTRL_VFFQE |
|
(hw->vlan_fail_q << GMAC_RXQCTRL_VFFQ_SHIFT);
|
writel(value, ioaddr + GMAC_RXQ_CTRL4);
|
value = GMAC_PACKET_FILTER_PR | GMAC_PACKET_FILTER_RA;
|
} else {
|
value = GMAC_PACKET_FILTER_PR | GMAC_PACKET_FILTER_PCF;
|
}
|
|
} else if ((dev->flags & IFF_ALLMULTI) ||
|
(netdev_mc_count(dev) > hw->multicast_filter_bins)) {
|
/* Pass all multi */
|
value |= GMAC_PACKET_FILTER_PM;
|
/* Set all the bits of the HASH tab */
|
memset(mc_filter, 0xff, sizeof(mc_filter));
|
} else if (!netdev_mc_empty(dev) && (dev->flags & IFF_MULTICAST)) {
|
struct netdev_hw_addr *ha;
|
|
/* Hash filter for multicast */
|
value |= GMAC_PACKET_FILTER_HMC;
|
|
netdev_for_each_mc_addr(ha, dev) {
|
/* The upper n bits of the calculated CRC are used to
|
* index the contents of the hash table. The number of
|
* bits used depends on the hardware configuration
|
* selected at core configuration time.
|
*/
|
u32 bit_nr = bitrev32(~crc32_le(~0, ha->addr,
|
ETH_ALEN)) >> (32 - mcbitslog2);
|
/* The most significant bit determines the register to
|
* use (H/L) while the other 5 bits determine the bit
|
* within the register.
|
*/
|
mc_filter[bit_nr >> 5] |= (1 << (bit_nr & 0x1f));
|
}
|
}
|
|
for (i = 0; i < numhashregs; i++)
|
writel(mc_filter[i], ioaddr + GMAC_HASH_TAB(i));
|
|
value |= GMAC_PACKET_FILTER_HPF;
|
|
/* Handle multiple unicast addresses */
|
if (netdev_uc_count(dev) > hw->unicast_filter_entries) {
|
/* Switch to promiscuous mode if more than 128 addrs
|
* are required
|
*/
|
value |= GMAC_PACKET_FILTER_PR;
|
} else {
|
struct netdev_hw_addr *ha;
|
int reg = 1;
|
|
netdev_for_each_uc_addr(ha, dev) {
|
dwmac4_set_umac_addr(hw, ha->addr, reg);
|
reg++;
|
}
|
|
while (reg < GMAC_MAX_PERFECT_ADDRESSES) {
|
writel(0, ioaddr + GMAC_ADDR_HIGH(reg));
|
writel(0, ioaddr + GMAC_ADDR_LOW(reg));
|
reg++;
|
}
|
}
|
|
/* VLAN filtering */
|
if (dev->features & NETIF_F_HW_VLAN_CTAG_FILTER)
|
value |= GMAC_PACKET_FILTER_VTFE;
|
|
writel(value, ioaddr + GMAC_PACKET_FILTER);
|
|
if (dev->flags & IFF_PROMISC && !hw->vlan_fail_q_en) {
|
if (!hw->promisc) {
|
hw->promisc = 1;
|
dwmac4_vlan_promisc_enable(dev, hw);
|
}
|
} else {
|
if (hw->promisc) {
|
hw->promisc = 0;
|
dwmac4_restore_hw_vlan_rx_fltr(dev, hw);
|
}
|
}
|
}
|
|
static void dwmac4_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
|
unsigned int fc, unsigned int pause_time,
|
u32 tx_cnt)
|
{
|
void __iomem *ioaddr = hw->pcsr;
|
unsigned int flow = 0;
|
u32 queue = 0;
|
|
pr_debug("GMAC Flow-Control:\n");
|
if (fc & FLOW_RX) {
|
pr_debug("\tReceive Flow-Control ON\n");
|
flow |= GMAC_RX_FLOW_CTRL_RFE;
|
} else {
|
pr_debug("\tReceive Flow-Control OFF\n");
|
}
|
writel(flow, ioaddr + GMAC_RX_FLOW_CTRL);
|
|
if (fc & FLOW_TX) {
|
pr_debug("\tTransmit Flow-Control ON\n");
|
|
if (duplex)
|
pr_debug("\tduplex mode: PAUSE %d\n", pause_time);
|
|
for (queue = 0; queue < tx_cnt; queue++) {
|
flow = GMAC_TX_FLOW_CTRL_TFE;
|
|
if (duplex)
|
flow |=
|
(pause_time << GMAC_TX_FLOW_CTRL_PT_SHIFT);
|
|
writel(flow, ioaddr + GMAC_QX_TX_FLOW_CTRL(queue));
|
}
|
} else {
|
for (queue = 0; queue < tx_cnt; queue++)
|
writel(0, ioaddr + GMAC_QX_TX_FLOW_CTRL(queue));
|
}
|
}
|
|
static void dwmac4_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral,
|
bool loopback)
|
{
|
dwmac_ctrl_ane(ioaddr, GMAC_PCS_BASE, ane, srgmi_ral, loopback);
|
}
|
|
static void dwmac4_rane(void __iomem *ioaddr, bool restart)
|
{
|
dwmac_rane(ioaddr, GMAC_PCS_BASE, restart);
|
}
|
|
static void dwmac4_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv)
|
{
|
dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv);
|
}
|
|
/* RGMII or SMII interface */
|
static void dwmac4_phystatus(void __iomem *ioaddr, struct stmmac_extra_stats *x)
|
{
|
u32 status;
|
|
status = readl(ioaddr + GMAC_PHYIF_CONTROL_STATUS);
|
x->irq_rgmii_n++;
|
|
/* Check the link status */
|
if (status & GMAC_PHYIF_CTRLSTATUS_LNKSTS) {
|
int speed_value;
|
|
x->pcs_link = 1;
|
|
speed_value = ((status & GMAC_PHYIF_CTRLSTATUS_SPEED) >>
|
GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT);
|
if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_125)
|
x->pcs_speed = SPEED_1000;
|
else if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_25)
|
x->pcs_speed = SPEED_100;
|
else
|
x->pcs_speed = SPEED_10;
|
|
x->pcs_duplex = (status & GMAC_PHYIF_CTRLSTATUS_LNKMOD_MASK);
|
|
pr_info("Link is Up - %d/%s\n", (int)x->pcs_speed,
|
x->pcs_duplex ? "Full" : "Half");
|
} else {
|
x->pcs_link = 0;
|
pr_info("Link is Down\n");
|
}
|
}
|
|
static int dwmac4_irq_mtl_status(struct mac_device_info *hw, u32 chan)
|
{
|
void __iomem *ioaddr = hw->pcsr;
|
u32 mtl_int_qx_status;
|
int ret = 0;
|
|
mtl_int_qx_status = readl(ioaddr + MTL_INT_STATUS);
|
|
/* Check MTL Interrupt */
|
if (mtl_int_qx_status & MTL_INT_QX(chan)) {
|
/* read Queue x Interrupt status */
|
u32 status = readl(ioaddr + MTL_CHAN_INT_CTRL(chan));
|
|
if (status & MTL_RX_OVERFLOW_INT) {
|
/* clear Interrupt */
|
writel(status | MTL_RX_OVERFLOW_INT,
|
ioaddr + MTL_CHAN_INT_CTRL(chan));
|
ret = CORE_IRQ_MTL_RX_OVERFLOW;
|
}
|
}
|
|
return ret;
|
}
|
|
static int dwmac4_irq_status(struct mac_device_info *hw,
|
struct stmmac_extra_stats *x)
|
{
|
void __iomem *ioaddr = hw->pcsr;
|
u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
|
u32 intr_enable = readl(ioaddr + GMAC_INT_EN);
|
int ret = 0;
|
|
/* Discard disabled bits */
|
intr_status &= intr_enable;
|
|
/* Not used events (e.g. MMC interrupts) are not handled. */
|
if ((intr_status & mmc_tx_irq))
|
x->mmc_tx_irq_n++;
|
if (unlikely(intr_status & mmc_rx_irq))
|
x->mmc_rx_irq_n++;
|
if (unlikely(intr_status & mmc_rx_csum_offload_irq))
|
x->mmc_rx_csum_offload_irq_n++;
|
/* Clear the PMT bits 5 and 6 by reading the PMT status reg */
|
if (unlikely(intr_status & pmt_irq)) {
|
readl(ioaddr + GMAC_PMT);
|
x->irq_receive_pmt_irq_n++;
|
}
|
|
/* MAC tx/rx EEE LPI entry/exit interrupts */
|
if (intr_status & lpi_irq) {
|
/* Clear LPI interrupt by reading MAC_LPI_Control_Status */
|
u32 status = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
|
|
if (status & GMAC4_LPI_CTRL_STATUS_TLPIEN) {
|
ret |= CORE_IRQ_TX_PATH_IN_LPI_MODE;
|
x->irq_tx_path_in_lpi_mode_n++;
|
}
|
if (status & GMAC4_LPI_CTRL_STATUS_TLPIEX) {
|
ret |= CORE_IRQ_TX_PATH_EXIT_LPI_MODE;
|
x->irq_tx_path_exit_lpi_mode_n++;
|
}
|
if (status & GMAC4_LPI_CTRL_STATUS_RLPIEN)
|
x->irq_rx_path_in_lpi_mode_n++;
|
if (status & GMAC4_LPI_CTRL_STATUS_RLPIEX)
|
x->irq_rx_path_exit_lpi_mode_n++;
|
}
|
|
dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x);
|
if (intr_status & PCS_RGSMIIIS_IRQ)
|
dwmac4_phystatus(ioaddr, x);
|
|
return ret;
|
}
|
|
static void dwmac4_debug(void __iomem *ioaddr, struct stmmac_extra_stats *x,
|
u32 rx_queues, u32 tx_queues)
|
{
|
u32 value;
|
u32 queue;
|
|
for (queue = 0; queue < tx_queues; queue++) {
|
value = readl(ioaddr + MTL_CHAN_TX_DEBUG(queue));
|
|
if (value & MTL_DEBUG_TXSTSFSTS)
|
x->mtl_tx_status_fifo_full++;
|
if (value & MTL_DEBUG_TXFSTS)
|
x->mtl_tx_fifo_not_empty++;
|
if (value & MTL_DEBUG_TWCSTS)
|
x->mmtl_fifo_ctrl++;
|
if (value & MTL_DEBUG_TRCSTS_MASK) {
|
u32 trcsts = (value & MTL_DEBUG_TRCSTS_MASK)
|
>> MTL_DEBUG_TRCSTS_SHIFT;
|
if (trcsts == MTL_DEBUG_TRCSTS_WRITE)
|
x->mtl_tx_fifo_read_ctrl_write++;
|
else if (trcsts == MTL_DEBUG_TRCSTS_TXW)
|
x->mtl_tx_fifo_read_ctrl_wait++;
|
else if (trcsts == MTL_DEBUG_TRCSTS_READ)
|
x->mtl_tx_fifo_read_ctrl_read++;
|
else
|
x->mtl_tx_fifo_read_ctrl_idle++;
|
}
|
if (value & MTL_DEBUG_TXPAUSED)
|
x->mac_tx_in_pause++;
|
}
|
|
for (queue = 0; queue < rx_queues; queue++) {
|
value = readl(ioaddr + MTL_CHAN_RX_DEBUG(queue));
|
|
if (value & MTL_DEBUG_RXFSTS_MASK) {
|
u32 rxfsts = (value & MTL_DEBUG_RXFSTS_MASK)
|
>> MTL_DEBUG_RRCSTS_SHIFT;
|
|
if (rxfsts == MTL_DEBUG_RXFSTS_FULL)
|
x->mtl_rx_fifo_fill_level_full++;
|
else if (rxfsts == MTL_DEBUG_RXFSTS_AT)
|
x->mtl_rx_fifo_fill_above_thresh++;
|
else if (rxfsts == MTL_DEBUG_RXFSTS_BT)
|
x->mtl_rx_fifo_fill_below_thresh++;
|
else
|
x->mtl_rx_fifo_fill_level_empty++;
|
}
|
if (value & MTL_DEBUG_RRCSTS_MASK) {
|
u32 rrcsts = (value & MTL_DEBUG_RRCSTS_MASK) >>
|
MTL_DEBUG_RRCSTS_SHIFT;
|
|
if (rrcsts == MTL_DEBUG_RRCSTS_FLUSH)
|
x->mtl_rx_fifo_read_ctrl_flush++;
|
else if (rrcsts == MTL_DEBUG_RRCSTS_RSTAT)
|
x->mtl_rx_fifo_read_ctrl_read_data++;
|
else if (rrcsts == MTL_DEBUG_RRCSTS_RDATA)
|
x->mtl_rx_fifo_read_ctrl_status++;
|
else
|
x->mtl_rx_fifo_read_ctrl_idle++;
|
}
|
if (value & MTL_DEBUG_RWCSTS)
|
x->mtl_rx_fifo_ctrl_active++;
|
}
|
|
/* GMAC debug */
|
value = readl(ioaddr + GMAC_DEBUG);
|
|
if (value & GMAC_DEBUG_TFCSTS_MASK) {
|
u32 tfcsts = (value & GMAC_DEBUG_TFCSTS_MASK)
|
>> GMAC_DEBUG_TFCSTS_SHIFT;
|
|
if (tfcsts == GMAC_DEBUG_TFCSTS_XFER)
|
x->mac_tx_frame_ctrl_xfer++;
|
else if (tfcsts == GMAC_DEBUG_TFCSTS_GEN_PAUSE)
|
x->mac_tx_frame_ctrl_pause++;
|
else if (tfcsts == GMAC_DEBUG_TFCSTS_WAIT)
|
x->mac_tx_frame_ctrl_wait++;
|
else
|
x->mac_tx_frame_ctrl_idle++;
|
}
|
if (value & GMAC_DEBUG_TPESTS)
|
x->mac_gmii_tx_proto_engine++;
|
if (value & GMAC_DEBUG_RFCFCSTS_MASK)
|
x->mac_rx_frame_ctrl_fifo = (value & GMAC_DEBUG_RFCFCSTS_MASK)
|
>> GMAC_DEBUG_RFCFCSTS_SHIFT;
|
if (value & GMAC_DEBUG_RPESTS)
|
x->mac_gmii_rx_proto_engine++;
|
}
|
|
static void dwmac4_set_mac_loopback(void __iomem *ioaddr, bool enable)
|
{
|
u32 value = readl(ioaddr + GMAC_CONFIG);
|
|
if (enable)
|
value |= GMAC_CONFIG_LM;
|
else
|
value &= ~GMAC_CONFIG_LM;
|
|
writel(value, ioaddr + GMAC_CONFIG);
|
}
|
|
static void dwmac4_update_vlan_hash(struct mac_device_info *hw, u32 hash,
|
__le16 perfect_match, bool is_double)
|
{
|
void __iomem *ioaddr = hw->pcsr;
|
u32 value;
|
|
writel(hash, ioaddr + GMAC_VLAN_HASH_TABLE);
|
|
value = readl(ioaddr + GMAC_VLAN_TAG);
|
|
if (hash) {
|
value |= GMAC_VLAN_VTHM | GMAC_VLAN_ETV;
|
if (is_double) {
|
value |= GMAC_VLAN_EDVLP;
|
value |= GMAC_VLAN_ESVL;
|
value |= GMAC_VLAN_DOVLTC;
|
}
|
|
writel(value, ioaddr + GMAC_VLAN_TAG);
|
} else if (perfect_match) {
|
u32 value = GMAC_VLAN_ETV;
|
|
if (is_double) {
|
value |= GMAC_VLAN_EDVLP;
|
value |= GMAC_VLAN_ESVL;
|
value |= GMAC_VLAN_DOVLTC;
|
}
|
|
writel(value | perfect_match, ioaddr + GMAC_VLAN_TAG);
|
} else {
|
value &= ~(GMAC_VLAN_VTHM | GMAC_VLAN_ETV);
|
value &= ~(GMAC_VLAN_EDVLP | GMAC_VLAN_ESVL);
|
value &= ~GMAC_VLAN_DOVLTC;
|
value &= ~GMAC_VLAN_VID;
|
|
writel(value, ioaddr + GMAC_VLAN_TAG);
|
}
|
}
|
|
static void dwmac4_sarc_configure(void __iomem *ioaddr, int val)
|
{
|
u32 value = readl(ioaddr + GMAC_CONFIG);
|
|
value &= ~GMAC_CONFIG_SARC;
|
value |= val << GMAC_CONFIG_SARC_SHIFT;
|
|
writel(value, ioaddr + GMAC_CONFIG);
|
}
|
|
static void dwmac4_enable_vlan(struct mac_device_info *hw, u32 type)
|
{
|
void __iomem *ioaddr = hw->pcsr;
|
u32 value;
|
|
value = readl(ioaddr + GMAC_VLAN_INCL);
|
value |= GMAC_VLAN_VLTI;
|
value |= GMAC_VLAN_CSVL; /* Only use SVLAN */
|
value &= ~GMAC_VLAN_VLC;
|
value |= (type << GMAC_VLAN_VLC_SHIFT) & GMAC_VLAN_VLC;
|
writel(value, ioaddr + GMAC_VLAN_INCL);
|
}
|
|
static void dwmac4_set_arp_offload(struct mac_device_info *hw, bool en,
|
u32 addr)
|
{
|
void __iomem *ioaddr = hw->pcsr;
|
u32 value;
|
|
writel(addr, ioaddr + GMAC_ARP_ADDR);
|
|
value = readl(ioaddr + GMAC_CONFIG);
|
if (en)
|
value |= GMAC_CONFIG_ARPEN;
|
else
|
value &= ~GMAC_CONFIG_ARPEN;
|
writel(value, ioaddr + GMAC_CONFIG);
|
}
|
|
static int dwmac4_config_l3_filter(struct mac_device_info *hw, u32 filter_no,
|
bool en, bool ipv6, bool sa, bool inv,
|
u32 match)
|
{
|
void __iomem *ioaddr = hw->pcsr;
|
u32 value;
|
|
value = readl(ioaddr + GMAC_PACKET_FILTER);
|
value |= GMAC_PACKET_FILTER_IPFE;
|
writel(value, ioaddr + GMAC_PACKET_FILTER);
|
|
value = readl(ioaddr + GMAC_L3L4_CTRL(filter_no));
|
|
/* For IPv6 not both SA/DA filters can be active */
|
if (ipv6) {
|
value |= GMAC_L3PEN0;
|
value &= ~(GMAC_L3SAM0 | GMAC_L3SAIM0);
|
value &= ~(GMAC_L3DAM0 | GMAC_L3DAIM0);
|
if (sa) {
|
value |= GMAC_L3SAM0;
|
if (inv)
|
value |= GMAC_L3SAIM0;
|
} else {
|
value |= GMAC_L3DAM0;
|
if (inv)
|
value |= GMAC_L3DAIM0;
|
}
|
} else {
|
value &= ~GMAC_L3PEN0;
|
if (sa) {
|
value |= GMAC_L3SAM0;
|
if (inv)
|
value |= GMAC_L3SAIM0;
|
} else {
|
value |= GMAC_L3DAM0;
|
if (inv)
|
value |= GMAC_L3DAIM0;
|
}
|
}
|
|
writel(value, ioaddr + GMAC_L3L4_CTRL(filter_no));
|
|
if (sa) {
|
writel(match, ioaddr + GMAC_L3_ADDR0(filter_no));
|
} else {
|
writel(match, ioaddr + GMAC_L3_ADDR1(filter_no));
|
}
|
|
if (!en)
|
writel(0, ioaddr + GMAC_L3L4_CTRL(filter_no));
|
|
return 0;
|
}
|
|
static int dwmac4_config_l4_filter(struct mac_device_info *hw, u32 filter_no,
|
bool en, bool udp, bool sa, bool inv,
|
u32 match)
|
{
|
void __iomem *ioaddr = hw->pcsr;
|
u32 value;
|
|
value = readl(ioaddr + GMAC_PACKET_FILTER);
|
value |= GMAC_PACKET_FILTER_IPFE;
|
writel(value, ioaddr + GMAC_PACKET_FILTER);
|
|
value = readl(ioaddr + GMAC_L3L4_CTRL(filter_no));
|
if (udp) {
|
value |= GMAC_L4PEN0;
|
} else {
|
value &= ~GMAC_L4PEN0;
|
}
|
|
value &= ~(GMAC_L4SPM0 | GMAC_L4SPIM0);
|
value &= ~(GMAC_L4DPM0 | GMAC_L4DPIM0);
|
if (sa) {
|
value |= GMAC_L4SPM0;
|
if (inv)
|
value |= GMAC_L4SPIM0;
|
} else {
|
value |= GMAC_L4DPM0;
|
if (inv)
|
value |= GMAC_L4DPIM0;
|
}
|
|
writel(value, ioaddr + GMAC_L3L4_CTRL(filter_no));
|
|
if (sa) {
|
value = match & GMAC_L4SP0;
|
} else {
|
value = (match << GMAC_L4DP0_SHIFT) & GMAC_L4DP0;
|
}
|
|
writel(value, ioaddr + GMAC_L4_ADDR(filter_no));
|
|
if (!en)
|
writel(0, ioaddr + GMAC_L3L4_CTRL(filter_no));
|
|
return 0;
|
}
|
|
#ifdef CONFIG_STMMAC_FULL
|
const struct stmmac_ops dwmac4_ops = {
|
.core_init = dwmac4_core_init,
|
.set_mac = stmmac_set_mac,
|
.rx_ipc = dwmac4_rx_ipc_enable,
|
.rx_queue_enable = dwmac4_rx_queue_enable,
|
.rx_queue_prio = dwmac4_rx_queue_priority,
|
.tx_queue_prio = dwmac4_tx_queue_priority,
|
.rx_queue_routing = dwmac4_rx_queue_routing,
|
.prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
|
.prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
|
.set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
|
.map_mtl_to_dma = dwmac4_map_mtl_dma,
|
.config_cbs = dwmac4_config_cbs,
|
.dump_regs = dwmac4_dump_regs,
|
.host_irq_status = dwmac4_irq_status,
|
.host_mtl_irq_status = dwmac4_irq_mtl_status,
|
.flow_ctrl = dwmac4_flow_ctrl,
|
.pmt = dwmac4_pmt,
|
.set_umac_addr = dwmac4_set_umac_addr,
|
.get_umac_addr = dwmac4_get_umac_addr,
|
.set_eee_mode = dwmac4_set_eee_mode,
|
.reset_eee_mode = dwmac4_reset_eee_mode,
|
.set_eee_timer = dwmac4_set_eee_timer,
|
.set_eee_pls = dwmac4_set_eee_pls,
|
.pcs_ctrl_ane = dwmac4_ctrl_ane,
|
.pcs_rane = dwmac4_rane,
|
.pcs_get_adv_lp = dwmac4_get_adv_lp,
|
.debug = dwmac4_debug,
|
.set_filter = dwmac4_set_filter,
|
.set_mac_loopback = dwmac4_set_mac_loopback,
|
.update_vlan_hash = dwmac4_update_vlan_hash,
|
.sarc_configure = dwmac4_sarc_configure,
|
.enable_vlan = dwmac4_enable_vlan,
|
.set_arp_offload = dwmac4_set_arp_offload,
|
.config_l3_filter = dwmac4_config_l3_filter,
|
.config_l4_filter = dwmac4_config_l4_filter,
|
.add_hw_vlan_rx_fltr = dwmac4_add_hw_vlan_rx_fltr,
|
.del_hw_vlan_rx_fltr = dwmac4_del_hw_vlan_rx_fltr,
|
.restore_hw_vlan_rx_fltr = dwmac4_restore_hw_vlan_rx_fltr,
|
};
|
#endif
|
|
const struct stmmac_ops dwmac410_ops = {
|
.core_init = dwmac4_core_init,
|
.set_mac = stmmac_dwmac4_set_mac,
|
.rx_ipc = dwmac4_rx_ipc_enable,
|
.rx_queue_enable = dwmac4_rx_queue_enable,
|
.rx_queue_prio = dwmac4_rx_queue_priority,
|
.tx_queue_prio = dwmac4_tx_queue_priority,
|
.rx_queue_routing = dwmac4_rx_queue_routing,
|
.prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
|
.prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
|
.set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
|
.map_mtl_to_dma = dwmac4_map_mtl_dma,
|
.config_cbs = dwmac4_config_cbs,
|
.dump_regs = dwmac4_dump_regs,
|
.host_irq_status = dwmac4_irq_status,
|
.host_mtl_irq_status = dwmac4_irq_mtl_status,
|
.flow_ctrl = dwmac4_flow_ctrl,
|
.pmt = dwmac4_pmt,
|
.set_umac_addr = dwmac4_set_umac_addr,
|
.get_umac_addr = dwmac4_get_umac_addr,
|
.set_eee_mode = dwmac4_set_eee_mode,
|
.reset_eee_mode = dwmac4_reset_eee_mode,
|
.set_eee_timer = dwmac4_set_eee_timer,
|
.set_eee_pls = dwmac4_set_eee_pls,
|
.pcs_ctrl_ane = dwmac4_ctrl_ane,
|
.pcs_rane = dwmac4_rane,
|
.pcs_get_adv_lp = dwmac4_get_adv_lp,
|
.debug = dwmac4_debug,
|
.set_filter = dwmac4_set_filter,
|
#ifdef CONFIG_STMMAC_FULL
|
.flex_pps_config = dwmac5_flex_pps_config,
|
#endif
|
.set_mac_loopback = dwmac4_set_mac_loopback,
|
.update_vlan_hash = dwmac4_update_vlan_hash,
|
.sarc_configure = dwmac4_sarc_configure,
|
.enable_vlan = dwmac4_enable_vlan,
|
.set_arp_offload = dwmac4_set_arp_offload,
|
.config_l3_filter = dwmac4_config_l3_filter,
|
.config_l4_filter = dwmac4_config_l4_filter,
|
#ifdef CONFIG_STMMAC_FULL
|
.est_configure = dwmac5_est_configure,
|
.fpe_configure = dwmac5_fpe_configure,
|
#endif
|
.add_hw_vlan_rx_fltr = dwmac4_add_hw_vlan_rx_fltr,
|
.del_hw_vlan_rx_fltr = dwmac4_del_hw_vlan_rx_fltr,
|
.restore_hw_vlan_rx_fltr = dwmac4_restore_hw_vlan_rx_fltr,
|
};
|
|
#ifdef CONFIG_STMMAC_FULL
|
const struct stmmac_ops dwmac510_ops = {
|
.core_init = dwmac4_core_init,
|
.set_mac = stmmac_dwmac4_set_mac,
|
.rx_ipc = dwmac4_rx_ipc_enable,
|
.rx_queue_enable = dwmac4_rx_queue_enable,
|
.rx_queue_prio = dwmac4_rx_queue_priority,
|
.tx_queue_prio = dwmac4_tx_queue_priority,
|
.rx_queue_routing = dwmac4_rx_queue_routing,
|
.prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
|
.prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
|
.set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
|
.map_mtl_to_dma = dwmac4_map_mtl_dma,
|
.config_cbs = dwmac4_config_cbs,
|
.dump_regs = dwmac4_dump_regs,
|
.host_irq_status = dwmac4_irq_status,
|
.host_mtl_irq_status = dwmac4_irq_mtl_status,
|
.flow_ctrl = dwmac4_flow_ctrl,
|
.pmt = dwmac4_pmt,
|
.set_umac_addr = dwmac4_set_umac_addr,
|
.get_umac_addr = dwmac4_get_umac_addr,
|
.set_eee_mode = dwmac4_set_eee_mode,
|
.reset_eee_mode = dwmac4_reset_eee_mode,
|
.set_eee_timer = dwmac4_set_eee_timer,
|
.set_eee_pls = dwmac4_set_eee_pls,
|
.pcs_ctrl_ane = dwmac4_ctrl_ane,
|
.pcs_rane = dwmac4_rane,
|
.pcs_get_adv_lp = dwmac4_get_adv_lp,
|
.debug = dwmac4_debug,
|
.set_filter = dwmac4_set_filter,
|
.safety_feat_config = dwmac5_safety_feat_config,
|
.safety_feat_irq_status = dwmac5_safety_feat_irq_status,
|
.safety_feat_dump = dwmac5_safety_feat_dump,
|
.rxp_config = dwmac5_rxp_config,
|
.flex_pps_config = dwmac5_flex_pps_config,
|
.set_mac_loopback = dwmac4_set_mac_loopback,
|
.update_vlan_hash = dwmac4_update_vlan_hash,
|
.sarc_configure = dwmac4_sarc_configure,
|
.enable_vlan = dwmac4_enable_vlan,
|
.set_arp_offload = dwmac4_set_arp_offload,
|
.config_l3_filter = dwmac4_config_l3_filter,
|
.config_l4_filter = dwmac4_config_l4_filter,
|
.est_configure = dwmac5_est_configure,
|
.fpe_configure = dwmac5_fpe_configure,
|
.add_hw_vlan_rx_fltr = dwmac4_add_hw_vlan_rx_fltr,
|
.del_hw_vlan_rx_fltr = dwmac4_del_hw_vlan_rx_fltr,
|
.restore_hw_vlan_rx_fltr = dwmac4_restore_hw_vlan_rx_fltr,
|
};
|
#endif
|
|
static u32 dwmac4_get_num_vlan(void __iomem *ioaddr)
|
{
|
u32 val, num_vlan;
|
|
val = readl(ioaddr + GMAC_HW_FEATURE3);
|
switch (val & GMAC_HW_FEAT_NRVF) {
|
case 0:
|
num_vlan = 1;
|
break;
|
case 1:
|
num_vlan = 4;
|
break;
|
case 2:
|
num_vlan = 8;
|
break;
|
case 3:
|
num_vlan = 16;
|
break;
|
case 4:
|
num_vlan = 24;
|
break;
|
case 5:
|
num_vlan = 32;
|
break;
|
default:
|
num_vlan = 1;
|
}
|
|
return num_vlan;
|
}
|
|
int dwmac4_setup(struct stmmac_priv *priv)
|
{
|
struct mac_device_info *mac = priv->hw;
|
|
dev_info(priv->device, "\tDWMAC4/5\n");
|
|
priv->dev->priv_flags |= IFF_UNICAST_FLT;
|
mac->pcsr = priv->ioaddr;
|
mac->multicast_filter_bins = priv->plat->multicast_filter_bins;
|
mac->unicast_filter_entries = priv->plat->unicast_filter_entries;
|
mac->mcast_bits_log2 = 0;
|
|
if (mac->multicast_filter_bins)
|
mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
|
|
mac->link.duplex = GMAC_CONFIG_DM;
|
mac->link.speed10 = GMAC_CONFIG_PS;
|
mac->link.speed100 = GMAC_CONFIG_FES | GMAC_CONFIG_PS;
|
mac->link.speed1000 = 0;
|
mac->link.speed_mask = GMAC_CONFIG_FES | GMAC_CONFIG_PS;
|
mac->mii.addr = GMAC_MDIO_ADDR;
|
mac->mii.data = GMAC_MDIO_DATA;
|
mac->mii.addr_shift = 21;
|
mac->mii.addr_mask = GENMASK(25, 21);
|
mac->mii.reg_shift = 16;
|
mac->mii.reg_mask = GENMASK(20, 16);
|
mac->mii.clk_csr_shift = 8;
|
mac->mii.clk_csr_mask = GENMASK(11, 8);
|
mac->num_vlan = dwmac4_get_num_vlan(priv->ioaddr);
|
|
return 0;
|
}
|
