// SPDX-License-Identifier: GPL-2.0-only
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/*******************************************************************************
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This is the driver for the MAC 10/100 on-chip Ethernet controller
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currently tested on all the ST boards based on STb7109 and stx7200 SoCs.
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DWC Ether MAC 10/100 Universal version 4.0 has been used for developing
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this code.
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This only implements the mac core functions for this chip.
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Copyright (C) 2007-2009 STMicroelectronics Ltd
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Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
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*******************************************************************************/
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#include <linux/crc32.h>
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#include <net/dsa.h>
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#include <asm/io.h>
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#include "stmmac.h"
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#include "dwmac100.h"
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static void dwmac100_core_init(struct mac_device_info *hw,
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struct net_device *dev)
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{
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void __iomem *ioaddr = hw->pcsr;
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u32 value = readl(ioaddr + MAC_CONTROL);
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value |= MAC_CORE_INIT;
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/* Clear ASTP bit because Ethernet switch tagging formats such as
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* Broadcom tags can look like invalid LLC/SNAP packets and cause the
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* hardware to truncate packets on reception.
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*/
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if (netdev_uses_dsa(dev))
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value &= ~MAC_CONTROL_ASTP;
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writel(value, ioaddr + MAC_CONTROL);
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#ifdef STMMAC_VLAN_TAG_USED
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writel(ETH_P_8021Q, ioaddr + MAC_VLAN1);
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#endif
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}
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static void dwmac100_dump_mac_regs(struct mac_device_info *hw, u32 *reg_space)
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{
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void __iomem *ioaddr = hw->pcsr;
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reg_space[MAC_CONTROL / 4] = readl(ioaddr + MAC_CONTROL);
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reg_space[MAC_ADDR_HIGH / 4] = readl(ioaddr + MAC_ADDR_HIGH);
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reg_space[MAC_ADDR_LOW / 4] = readl(ioaddr + MAC_ADDR_LOW);
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reg_space[MAC_HASH_HIGH / 4] = readl(ioaddr + MAC_HASH_HIGH);
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reg_space[MAC_HASH_LOW / 4] = readl(ioaddr + MAC_HASH_LOW);
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reg_space[MAC_FLOW_CTRL / 4] = readl(ioaddr + MAC_FLOW_CTRL);
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reg_space[MAC_VLAN1 / 4] = readl(ioaddr + MAC_VLAN1);
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reg_space[MAC_VLAN2 / 4] = readl(ioaddr + MAC_VLAN2);
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}
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static int dwmac100_rx_ipc_enable(struct mac_device_info *hw)
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{
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return 0;
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}
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static int dwmac100_irq_status(struct mac_device_info *hw,
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struct stmmac_extra_stats *x)
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{
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return 0;
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}
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static void dwmac100_set_umac_addr(struct mac_device_info *hw,
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unsigned char *addr,
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unsigned int reg_n)
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{
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void __iomem *ioaddr = hw->pcsr;
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stmmac_set_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
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}
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static void dwmac100_get_umac_addr(struct mac_device_info *hw,
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unsigned char *addr,
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unsigned int reg_n)
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{
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void __iomem *ioaddr = hw->pcsr;
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stmmac_get_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
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}
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static void dwmac100_set_filter(struct mac_device_info *hw,
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struct net_device *dev)
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{
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void __iomem *ioaddr = (void __iomem *)dev->base_addr;
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u32 value = readl(ioaddr + MAC_CONTROL);
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if (dev->flags & IFF_PROMISC) {
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value |= MAC_CONTROL_PR;
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value &= ~(MAC_CONTROL_PM | MAC_CONTROL_IF | MAC_CONTROL_HO |
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MAC_CONTROL_HP);
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} else if ((netdev_mc_count(dev) > HASH_TABLE_SIZE)
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|| (dev->flags & IFF_ALLMULTI)) {
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value |= MAC_CONTROL_PM;
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value &= ~(MAC_CONTROL_PR | MAC_CONTROL_IF | MAC_CONTROL_HO);
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writel(0xffffffff, ioaddr + MAC_HASH_HIGH);
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writel(0xffffffff, ioaddr + MAC_HASH_LOW);
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} else if (netdev_mc_empty(dev)) { /* no multicast */
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value &= ~(MAC_CONTROL_PM | MAC_CONTROL_PR | MAC_CONTROL_IF |
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MAC_CONTROL_HO | MAC_CONTROL_HP);
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} else {
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u32 mc_filter[2];
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struct netdev_hw_addr *ha;
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/* Perfect filter mode for physical address and Hash
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* filter for multicast
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*/
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value |= MAC_CONTROL_HP;
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value &= ~(MAC_CONTROL_PM | MAC_CONTROL_PR |
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MAC_CONTROL_IF | MAC_CONTROL_HO);
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memset(mc_filter, 0, sizeof(mc_filter));
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netdev_for_each_mc_addr(ha, dev) {
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/* The upper 6 bits of the calculated CRC are used to
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* index the contens of the hash table
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*/
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int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
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/* The most significant bit determines the register to
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* use (H/L) while the other 5 bits determine the bit
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* within the register.
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*/
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mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
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}
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writel(mc_filter[0], ioaddr + MAC_HASH_LOW);
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writel(mc_filter[1], ioaddr + MAC_HASH_HIGH);
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}
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writel(value, ioaddr + MAC_CONTROL);
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}
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static void dwmac100_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
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unsigned int fc, unsigned int pause_time,
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u32 tx_cnt)
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{
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void __iomem *ioaddr = hw->pcsr;
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unsigned int flow = MAC_FLOW_CTRL_ENABLE;
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if (duplex)
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flow |= (pause_time << MAC_FLOW_CTRL_PT_SHIFT);
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writel(flow, ioaddr + MAC_FLOW_CTRL);
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}
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/* No PMT module supported on ST boards with this Eth chip. */
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static void dwmac100_pmt(struct mac_device_info *hw, unsigned long mode)
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{
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return;
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}
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static void dwmac100_set_mac_loopback(void __iomem *ioaddr, bool enable)
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{
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u32 value = readl(ioaddr + MAC_CONTROL);
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if (enable)
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value |= MAC_CONTROL_OM;
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else
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value &= ~MAC_CONTROL_OM;
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writel(value, ioaddr + MAC_CONTROL);
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}
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const struct stmmac_ops dwmac100_ops = {
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.core_init = dwmac100_core_init,
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.set_mac = stmmac_set_mac,
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.rx_ipc = dwmac100_rx_ipc_enable,
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.dump_regs = dwmac100_dump_mac_regs,
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.host_irq_status = dwmac100_irq_status,
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.set_filter = dwmac100_set_filter,
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.flow_ctrl = dwmac100_flow_ctrl,
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.pmt = dwmac100_pmt,
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.set_umac_addr = dwmac100_set_umac_addr,
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.get_umac_addr = dwmac100_get_umac_addr,
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.set_mac_loopback = dwmac100_set_mac_loopback,
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};
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int dwmac100_setup(struct stmmac_priv *priv)
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{
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struct mac_device_info *mac = priv->hw;
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dev_info(priv->device, "\tDWMAC100\n");
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mac->pcsr = priv->ioaddr;
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mac->link.duplex = MAC_CONTROL_F;
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mac->link.speed10 = 0;
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mac->link.speed100 = 0;
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mac->link.speed1000 = 0;
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mac->link.speed_mask = MAC_CONTROL_PS;
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mac->mii.addr = MAC_MII_ADDR;
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mac->mii.data = MAC_MII_DATA;
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mac->mii.addr_shift = 11;
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mac->mii.addr_mask = 0x0000F800;
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mac->mii.reg_shift = 6;
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mac->mii.reg_mask = 0x000007C0;
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mac->mii.clk_csr_shift = 2;
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mac->mii.clk_csr_mask = GENMASK(5, 2);
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return 0;
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}
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