/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2020, Intel Corporation
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* DWMAC Intel header file
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*/
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#ifndef __DWMAC_INTEL_H__
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#define __DWMAC_INTEL_H__
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#define POLL_DELAY_US 8
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/* SERDES Register */
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#define SERDES_GSR0 0x5 /* Global Status Reg0 */
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#define SERDES_GCR0 0xb /* Global Configuration Reg0 */
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/* SERDES defines */
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#define SERDES_PLL_CLK BIT(0) /* PLL clk valid signal */
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#define SERDES_RST BIT(2) /* Serdes Reset */
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#define SERDES_PWR_ST_MASK GENMASK(6, 4) /* Serdes Power state*/
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#define SERDES_PWR_ST_SHIFT 4
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#define SERDES_PWR_ST_P0 0x0
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#define SERDES_PWR_ST_P3 0x3
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#endif /* __DWMAC_INTEL_H__ */
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