/* SPDX-License-Identifier: GPL-2.0-only */
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/*******************************************************************************
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Header File to describe the DMA descriptors and related definitions.
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This is for DWMAC100 and 1000 cores.
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Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
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*******************************************************************************/
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#ifndef __DESCS_H__
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#define __DESCS_H__
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#include <linux/bitops.h>
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/* Normal receive descriptor defines */
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/* RDES0 */
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#define RDES0_PAYLOAD_CSUM_ERR BIT(0)
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#define RDES0_CRC_ERROR BIT(1)
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#define RDES0_DRIBBLING BIT(2)
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#define RDES0_MII_ERROR BIT(3)
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#define RDES0_RECEIVE_WATCHDOG BIT(4)
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#define RDES0_FRAME_TYPE BIT(5)
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#define RDES0_COLLISION BIT(6)
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#define RDES0_IPC_CSUM_ERROR BIT(7)
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#define RDES0_LAST_DESCRIPTOR BIT(8)
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#define RDES0_FIRST_DESCRIPTOR BIT(9)
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#define RDES0_VLAN_TAG BIT(10)
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#define RDES0_OVERFLOW_ERROR BIT(11)
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#define RDES0_LENGTH_ERROR BIT(12)
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#define RDES0_SA_FILTER_FAIL BIT(13)
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#define RDES0_DESCRIPTOR_ERROR BIT(14)
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#define RDES0_ERROR_SUMMARY BIT(15)
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#define RDES0_FRAME_LEN_MASK GENMASK(29, 16)
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#define RDES0_FRAME_LEN_SHIFT 16
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#define RDES0_DA_FILTER_FAIL BIT(30)
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#define RDES0_OWN BIT(31)
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/* RDES1 */
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#define RDES1_BUFFER1_SIZE_MASK GENMASK(10, 0)
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#define RDES1_BUFFER2_SIZE_MASK GENMASK(21, 11)
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#define RDES1_BUFFER2_SIZE_SHIFT 11
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#define RDES1_SECOND_ADDRESS_CHAINED BIT(24)
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#define RDES1_END_RING BIT(25)
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#define RDES1_DISABLE_IC BIT(31)
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/* Enhanced receive descriptor defines */
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/* RDES0 (similar to normal RDES) */
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#define ERDES0_RX_MAC_ADDR BIT(0)
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/* RDES1: completely differ from normal desc definitions */
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#define ERDES1_BUFFER1_SIZE_MASK GENMASK(12, 0)
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#define ERDES1_SECOND_ADDRESS_CHAINED BIT(14)
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#define ERDES1_END_RING BIT(15)
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#define ERDES1_BUFFER2_SIZE_MASK GENMASK(28, 16)
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#define ERDES1_BUFFER2_SIZE_SHIFT 16
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#define ERDES1_DISABLE_IC BIT(31)
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/* Normal transmit descriptor defines */
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/* TDES0 */
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#define TDES0_DEFERRED BIT(0)
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#define TDES0_UNDERFLOW_ERROR BIT(1)
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#define TDES0_EXCESSIVE_DEFERRAL BIT(2)
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#define TDES0_COLLISION_COUNT_MASK GENMASK(6, 3)
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#define TDES0_VLAN_FRAME BIT(7)
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#define TDES0_EXCESSIVE_COLLISIONS BIT(8)
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#define TDES0_LATE_COLLISION BIT(9)
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#define TDES0_NO_CARRIER BIT(10)
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#define TDES0_LOSS_CARRIER BIT(11)
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#define TDES0_PAYLOAD_ERROR BIT(12)
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#define TDES0_FRAME_FLUSHED BIT(13)
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#define TDES0_JABBER_TIMEOUT BIT(14)
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#define TDES0_ERROR_SUMMARY BIT(15)
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#define TDES0_IP_HEADER_ERROR BIT(16)
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#define TDES0_TIME_STAMP_STATUS BIT(17)
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#define TDES0_OWN ((u32)BIT(31)) /* silence sparse */
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/* TDES1 */
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#define TDES1_BUFFER1_SIZE_MASK GENMASK(10, 0)
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#define TDES1_BUFFER2_SIZE_MASK GENMASK(21, 11)
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#define TDES1_BUFFER2_SIZE_SHIFT 11
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#define TDES1_TIME_STAMP_ENABLE BIT(22)
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#define TDES1_DISABLE_PADDING BIT(23)
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#define TDES1_SECOND_ADDRESS_CHAINED BIT(24)
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#define TDES1_END_RING BIT(25)
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#define TDES1_CRC_DISABLE BIT(26)
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#define TDES1_CHECKSUM_INSERTION_MASK GENMASK(28, 27)
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#define TDES1_CHECKSUM_INSERTION_SHIFT 27
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#define TDES1_FIRST_SEGMENT BIT(29)
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#define TDES1_LAST_SEGMENT BIT(30)
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#define TDES1_INTERRUPT BIT(31)
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/* Enhanced transmit descriptor defines */
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/* TDES0 */
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#define ETDES0_DEFERRED BIT(0)
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#define ETDES0_UNDERFLOW_ERROR BIT(1)
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#define ETDES0_EXCESSIVE_DEFERRAL BIT(2)
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#define ETDES0_COLLISION_COUNT_MASK GENMASK(6, 3)
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#define ETDES0_VLAN_FRAME BIT(7)
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#define ETDES0_EXCESSIVE_COLLISIONS BIT(8)
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#define ETDES0_LATE_COLLISION BIT(9)
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#define ETDES0_NO_CARRIER BIT(10)
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#define ETDES0_LOSS_CARRIER BIT(11)
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#define ETDES0_PAYLOAD_ERROR BIT(12)
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#define ETDES0_FRAME_FLUSHED BIT(13)
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#define ETDES0_JABBER_TIMEOUT BIT(14)
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#define ETDES0_ERROR_SUMMARY BIT(15)
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#define ETDES0_IP_HEADER_ERROR BIT(16)
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#define ETDES0_TIME_STAMP_STATUS BIT(17)
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#define ETDES0_SECOND_ADDRESS_CHAINED BIT(20)
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#define ETDES0_END_RING BIT(21)
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#define ETDES0_CHECKSUM_INSERTION_MASK GENMASK(23, 22)
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#define ETDES0_CHECKSUM_INSERTION_SHIFT 22
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#define ETDES0_TIME_STAMP_ENABLE BIT(25)
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#define ETDES0_DISABLE_PADDING BIT(26)
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#define ETDES0_CRC_DISABLE BIT(27)
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#define ETDES0_FIRST_SEGMENT BIT(28)
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#define ETDES0_LAST_SEGMENT BIT(29)
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#define ETDES0_INTERRUPT BIT(30)
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#define ETDES0_OWN ((u32)BIT(31)) /* silence sparse */
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/* TDES1 */
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#define ETDES1_BUFFER1_SIZE_MASK GENMASK(12, 0)
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#define ETDES1_BUFFER2_SIZE_MASK GENMASK(28, 16)
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#define ETDES1_BUFFER2_SIZE_SHIFT 16
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/* Extended Receive descriptor definitions */
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#define ERDES4_IP_PAYLOAD_TYPE_MASK GENMASK(6, 2)
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#define ERDES4_IP_HDR_ERR BIT(3)
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#define ERDES4_IP_PAYLOAD_ERR BIT(4)
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#define ERDES4_IP_CSUM_BYPASSED BIT(5)
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#define ERDES4_IPV4_PKT_RCVD BIT(6)
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#define ERDES4_IPV6_PKT_RCVD BIT(7)
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#define ERDES4_MSG_TYPE_MASK GENMASK(11, 8)
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#define ERDES4_PTP_FRAME_TYPE BIT(12)
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#define ERDES4_PTP_VER BIT(13)
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#define ERDES4_TIMESTAMP_DROPPED BIT(14)
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#define ERDES4_AV_PKT_RCVD BIT(16)
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#define ERDES4_AV_TAGGED_PKT_RCVD BIT(17)
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#define ERDES4_VLAN_TAG_PRI_VAL_MASK GENMASK(20, 18)
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#define ERDES4_L3_FILTER_MATCH BIT(24)
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#define ERDES4_L4_FILTER_MATCH BIT(25)
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#define ERDES4_L3_L4_FILT_NO_MATCH_MASK GENMASK(27, 26)
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/* Extended RDES4 message type definitions */
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#define RDES_EXT_NO_PTP 0x0
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#define RDES_EXT_SYNC 0x1
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#define RDES_EXT_FOLLOW_UP 0x2
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#define RDES_EXT_DELAY_REQ 0x3
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#define RDES_EXT_DELAY_RESP 0x4
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#define RDES_EXT_PDELAY_REQ 0x5
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#define RDES_EXT_PDELAY_RESP 0x6
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#define RDES_EXT_PDELAY_FOLLOW_UP 0x7
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#define RDES_PTP_ANNOUNCE 0x8
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#define RDES_PTP_MANAGEMENT 0x9
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#define RDES_PTP_SIGNALING 0xa
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#define RDES_PTP_PKT_RESERVED_TYPE 0xf
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/* Basic descriptor structure for normal and alternate descriptors */
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struct dma_desc {
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__le32 des0;
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__le32 des1;
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__le32 des2;
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__le32 des3;
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};
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/* Extended descriptor structure (e.g. >= databook 3.50a) */
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struct dma_extended_desc {
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struct dma_desc basic; /* Basic descriptors */
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__le32 des4; /* Extended Status */
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__le32 des5; /* Reserved */
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__le32 des6; /* Tx/Rx Timestamp Low */
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__le32 des7; /* Tx/Rx Timestamp High */
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};
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/* Enhanced descriptor for TBS */
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struct dma_edesc {
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__le32 des4;
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__le32 des5;
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__le32 des6;
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__le32 des7;
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struct dma_desc basic;
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};
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/* Transmit checksum insertion control */
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#define TX_CIC_FULL 3 /* Include IP header and pseudoheader */
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#endif /* __DESCS_H__ */
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