/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _NB8800_H_
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#define _NB8800_H_
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#include <linux/types.h>
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#include <linux/skbuff.h>
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#include <linux/phy.h>
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#include <linux/clk.h>
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#include <linux/bitops.h>
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#define RX_DESC_COUNT 256
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#define TX_DESC_COUNT 256
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#define NB8800_DESC_LOW 4
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#define RX_BUF_SIZE 1552
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#define RX_COPYBREAK 256
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#define RX_COPYHDR 128
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#define MAX_MDC_CLOCK 2500000
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/* Stargate Solutions SSN8800 core registers */
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#define NB8800_TX_CTL1 0x000
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#define TX_TPD BIT(5)
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#define TX_APPEND_FCS BIT(4)
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#define TX_PAD_EN BIT(3)
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#define TX_RETRY_EN BIT(2)
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#define TX_EN BIT(0)
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#define NB8800_TX_CTL2 0x001
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#define NB8800_RX_CTL 0x004
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#define RX_BC_DISABLE BIT(7)
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#define RX_RUNT BIT(6)
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#define RX_AF_EN BIT(5)
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#define RX_PAUSE_EN BIT(3)
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#define RX_SEND_CRC BIT(2)
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#define RX_PAD_STRIP BIT(1)
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#define RX_EN BIT(0)
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#define NB8800_RANDOM_SEED 0x008
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#define NB8800_TX_SDP 0x14
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#define NB8800_TX_TPDP1 0x18
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#define NB8800_TX_TPDP2 0x19
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#define NB8800_SLOT_TIME 0x1c
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#define NB8800_MDIO_CMD 0x020
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#define MDIO_CMD_GO BIT(31)
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#define MDIO_CMD_WR BIT(26)
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#define MDIO_CMD_ADDR(x) ((x) << 21)
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#define MDIO_CMD_REG(x) ((x) << 16)
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#define MDIO_CMD_DATA(x) ((x) << 0)
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#define NB8800_MDIO_STS 0x024
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#define MDIO_STS_ERR BIT(31)
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#define NB8800_MC_ADDR(i) (0x028 + (i))
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#define NB8800_MC_INIT 0x02e
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#define NB8800_UC_ADDR(i) (0x03c + (i))
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#define NB8800_MAC_MODE 0x044
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#define RGMII_MODE BIT(7)
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#define HALF_DUPLEX BIT(4)
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#define BURST_EN BIT(3)
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#define LOOPBACK_EN BIT(2)
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#define GMAC_MODE BIT(0)
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#define NB8800_IC_THRESHOLD 0x050
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#define NB8800_PE_THRESHOLD 0x051
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#define NB8800_PF_THRESHOLD 0x052
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#define NB8800_TX_BUFSIZE 0x054
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#define NB8800_FIFO_CTL 0x056
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#define NB8800_PQ1 0x060
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#define NB8800_PQ2 0x061
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#define NB8800_SRC_ADDR(i) (0x06a + (i))
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#define NB8800_STAT_DATA 0x078
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#define NB8800_STAT_INDEX 0x07c
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#define NB8800_STAT_CLEAR 0x07d
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#define NB8800_SLEEP_MODE 0x07e
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#define SLEEP_MODE BIT(0)
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#define NB8800_WAKEUP 0x07f
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#define WAKEUP BIT(0)
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/* Aurora NB8800 host interface registers */
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#define NB8800_TXC_CR 0x100
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#define TCR_LK BIT(12)
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#define TCR_DS BIT(11)
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#define TCR_BTS(x) (((x) & 0x7) << 8)
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#define TCR_DIE BIT(7)
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#define TCR_TFI(x) (((x) & 0x7) << 4)
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#define TCR_LE BIT(3)
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#define TCR_RS BIT(2)
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#define TCR_DM BIT(1)
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#define TCR_EN BIT(0)
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#define NB8800_TXC_SR 0x104
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#define TSR_DE BIT(3)
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#define TSR_DI BIT(2)
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#define TSR_TO BIT(1)
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#define TSR_TI BIT(0)
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#define NB8800_TX_SAR 0x108
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#define NB8800_TX_DESC_ADDR 0x10c
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#define NB8800_TX_REPORT_ADDR 0x110
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#define TX_BYTES_TRANSFERRED(x) (((x) >> 16) & 0xffff)
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#define TX_FIRST_DEFERRAL BIT(7)
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#define TX_EARLY_COLLISIONS(x) (((x) >> 3) & 0xf)
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#define TX_LATE_COLLISION BIT(2)
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#define TX_PACKET_DROPPED BIT(1)
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#define TX_FIFO_UNDERRUN BIT(0)
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#define IS_TX_ERROR(r) ((r) & 0x07)
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#define NB8800_TX_FIFO_SR 0x114
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#define NB8800_TX_ITR 0x118
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#define NB8800_RXC_CR 0x200
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#define RCR_FL BIT(13)
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#define RCR_LK BIT(12)
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#define RCR_DS BIT(11)
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#define RCR_BTS(x) (((x) & 7) << 8)
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#define RCR_DIE BIT(7)
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#define RCR_RFI(x) (((x) & 7) << 4)
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#define RCR_LE BIT(3)
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#define RCR_RS BIT(2)
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#define RCR_DM BIT(1)
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#define RCR_EN BIT(0)
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#define NB8800_RXC_SR 0x204
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#define RSR_DE BIT(3)
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#define RSR_DI BIT(2)
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#define RSR_RO BIT(1)
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#define RSR_RI BIT(0)
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#define NB8800_RX_SAR 0x208
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#define NB8800_RX_DESC_ADDR 0x20c
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#define NB8800_RX_REPORT_ADDR 0x210
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#define RX_BYTES_TRANSFERRED(x) (((x) >> 16) & 0xFFFF)
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#define RX_MULTICAST_PKT BIT(9)
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#define RX_BROADCAST_PKT BIT(8)
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#define RX_LENGTH_ERR BIT(7)
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#define RX_FCS_ERR BIT(6)
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#define RX_RUNT_PKT BIT(5)
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#define RX_FIFO_OVERRUN BIT(4)
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#define RX_LATE_COLLISION BIT(3)
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#define RX_ALIGNMENT_ERROR BIT(2)
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#define RX_ERROR_MASK 0xfc
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#define IS_RX_ERROR(r) ((r) & RX_ERROR_MASK)
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#define NB8800_RX_FIFO_SR 0x214
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#define NB8800_RX_ITR 0x218
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/* Sigma Designs SMP86xx additional registers */
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#define NB8800_TANGOX_PAD_MODE 0x400
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#define PAD_MODE_MASK 0x7
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#define PAD_MODE_MII 0x0
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#define PAD_MODE_RGMII 0x1
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#define PAD_MODE_GTX_CLK_INV BIT(3)
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#define PAD_MODE_GTX_CLK_DELAY BIT(4)
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#define NB8800_TANGOX_MDIO_CLKDIV 0x420
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#define NB8800_TANGOX_RESET 0x424
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/* Hardware DMA descriptor */
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struct nb8800_dma_desc {
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u32 s_addr; /* start address */
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u32 n_addr; /* next descriptor address */
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u32 r_addr; /* report address */
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u32 config;
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} __aligned(8);
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#define DESC_ID BIT(23)
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#define DESC_EOC BIT(22)
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#define DESC_EOF BIT(21)
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#define DESC_LK BIT(20)
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#define DESC_DS BIT(19)
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#define DESC_BTS(x) (((x) & 0x7) << 16)
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/* DMA descriptor and associated data for rx.
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* Allocated from coherent memory.
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*/
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struct nb8800_rx_desc {
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/* DMA descriptor */
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struct nb8800_dma_desc desc;
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/* Status report filled in by hardware */
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u32 report;
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};
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/* Address of buffer on rx ring */
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struct nb8800_rx_buf {
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struct page *page;
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unsigned long offset;
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};
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/* DMA descriptors and associated data for tx.
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* Allocated from coherent memory.
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*/
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struct nb8800_tx_desc {
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/* DMA descriptor. The second descriptor is used if packet
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* data is unaligned.
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*/
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struct nb8800_dma_desc desc[2];
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/* Status report filled in by hardware */
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u32 report;
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/* Bounce buffer for initial unaligned part of packet */
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u8 buf[8] __aligned(8);
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};
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/* Packet in tx queue */
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struct nb8800_tx_buf {
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/* Currently queued skb */
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struct sk_buff *skb;
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/* DMA address of the first descriptor */
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dma_addr_t dma_desc;
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/* DMA address of packet data */
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dma_addr_t dma_addr;
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/* Length of DMA mapping, less than skb->len if alignment
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* buffer is used.
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*/
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unsigned int dma_len;
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/* Number of packets in chain starting here */
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unsigned int chain_len;
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/* Packet chain ready to be submitted to hardware */
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bool ready;
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};
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struct nb8800_priv {
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struct napi_struct napi;
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void __iomem *base;
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/* RX DMA descriptors */
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struct nb8800_rx_desc *rx_descs;
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/* RX buffers referenced by DMA descriptors */
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struct nb8800_rx_buf *rx_bufs;
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/* Current end of chain */
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u32 rx_eoc;
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/* Value for rx interrupt time register in NAPI interrupt mode */
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u32 rx_itr_irq;
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/* Value for rx interrupt time register in NAPI poll mode */
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u32 rx_itr_poll;
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/* Value for config field of rx DMA descriptors */
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u32 rx_dma_config;
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/* TX DMA descriptors */
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struct nb8800_tx_desc *tx_descs;
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/* TX packet queue */
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struct nb8800_tx_buf *tx_bufs;
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/* Number of free tx queue entries */
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atomic_t tx_free;
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/* First free tx queue entry */
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u32 tx_next;
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/* Next buffer to transmit */
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u32 tx_queue;
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/* Start of current packet chain */
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struct nb8800_tx_buf *tx_chain;
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/* Next buffer to reclaim */
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u32 tx_done;
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/* Lock for DMA activation */
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spinlock_t tx_lock;
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struct mii_bus *mii_bus;
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struct device_node *phy_node;
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/* PHY connection type from DT */
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phy_interface_t phy_mode;
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/* Current link status */
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int speed;
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int duplex;
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int link;
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/* Pause settings */
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bool pause_aneg;
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bool pause_rx;
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bool pause_tx;
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/* DMA base address of rx descriptors, see rx_descs above */
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dma_addr_t rx_desc_dma;
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/* DMA base address of tx descriptors, see tx_descs above */
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dma_addr_t tx_desc_dma;
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struct clk *clk;
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};
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struct nb8800_ops {
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int (*init)(struct net_device *dev);
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int (*reset)(struct net_device *dev);
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};
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#endif /* _NB8800_H_ */
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