/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
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/*
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*
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* (C) COPYRIGHT 2019-2022 ARM Limited. All rights reserved.
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*
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* This program is free software and is provided to you under the terms of the
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* GNU General Public License version 2 as published by the Free Software
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* Foundation, and any use by you of this program is subject to the terms
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* of such GNU license.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you can access it online at
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* http://www.gnu.org/licenses/gpl-2.0.html.
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*
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*/
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#ifndef _UAPI_KBASE_GPU_REGMAP_H_
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#define _UAPI_KBASE_GPU_REGMAP_H_
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#if MALI_USE_CSF
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#include "backend/mali_kbase_gpu_regmap_csf.h"
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#else
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#include "backend/mali_kbase_gpu_regmap_jm.h"
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#endif /* !MALI_USE_CSF */
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/* Begin Register Offsets */
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/* GPU control registers */
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#define GPU_CONTROL_BASE 0x0000
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#define GPU_CONTROL_REG(r) (GPU_CONTROL_BASE + (r))
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#define GPU_ID 0x000 /* (RO) GPU and revision identifier */
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#define GPU_IRQ_CLEAR 0x024 /* (WO) */
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#define GPU_IRQ_STATUS 0x02C /* (RO) */
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#define SHADER_READY_LO 0x140 /* (RO) Shader core ready bitmap, low word */
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#define SHADER_READY_HI 0x144 /* (RO) Shader core ready bitmap, high word */
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#define TILER_READY_LO 0x150 /* (RO) Tiler core ready bitmap, low word */
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#define TILER_READY_HI 0x154 /* (RO) Tiler core ready bitmap, high word */
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#define L2_READY_LO 0x160 /* (RO) Level 2 cache ready bitmap, low word */
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#define L2_READY_HI 0x164 /* (RO) Level 2 cache ready bitmap, high word */
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#define SHADER_PWRON_LO 0x180 /* (WO) Shader core power on bitmap, low word */
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#define SHADER_PWRON_HI 0x184 /* (WO) Shader core power on bitmap, high word */
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#define TILER_PWRON_LO 0x190 /* (WO) Tiler core power on bitmap, low word */
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#define TILER_PWRON_HI 0x194 /* (WO) Tiler core power on bitmap, high word */
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#define L2_PWRON_LO 0x1A0 /* (WO) Level 2 cache power on bitmap, low word */
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#define L2_PWRON_HI 0x1A4 /* (WO) Level 2 cache power on bitmap, high word */
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/* Job control registers */
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#define JOB_CONTROL_BASE 0x1000
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#define JOB_CONTROL_REG(r) (JOB_CONTROL_BASE + (r))
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#define JOB_IRQ_CLEAR 0x004 /* Interrupt clear register */
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#define JOB_IRQ_MASK 0x008 /* Interrupt mask register */
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#define JOB_IRQ_STATUS 0x00C /* Interrupt status register */
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/* MMU control registers */
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#define MEMORY_MANAGEMENT_BASE 0x2000
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#define MMU_REG(r) (MEMORY_MANAGEMENT_BASE + (r))
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#define MMU_IRQ_RAWSTAT 0x000 /* (RW) Raw interrupt status register */
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#define MMU_IRQ_CLEAR 0x004 /* (WO) Interrupt clear register */
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#define MMU_IRQ_MASK 0x008 /* (RW) Interrupt mask register */
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#define MMU_IRQ_STATUS 0x00C /* (RO) Interrupt status register */
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#define MMU_AS0 0x400 /* Configuration registers for address space 0 */
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/* MMU address space control registers */
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#define MMU_AS_REG(n, r) (MMU_REG(MMU_AS0 + ((n) << 6)) + (r))
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#define AS_TRANSTAB_LO 0x00 /* (RW) Translation Table Base Address for address space n, low word */
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#define AS_TRANSTAB_HI 0x04 /* (RW) Translation Table Base Address for address space n, high word */
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#define AS_MEMATTR_LO 0x08 /* (RW) Memory attributes for address space n, low word. */
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#define AS_MEMATTR_HI 0x0C /* (RW) Memory attributes for address space n, high word. */
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#define AS_COMMAND 0x18 /* (WO) MMU command register for address space n */
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/* (RW) Translation table configuration for address space n, low word */
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#define AS_TRANSCFG_LO 0x30
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/* (RW) Translation table configuration for address space n, high word */
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#define AS_TRANSCFG_HI 0x34
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#endif /* _UAPI_KBASE_GPU_REGMAP_H_ */
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