/*
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* Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef _SFC_H
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#define _SFC_H
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#define SFC_VER_3 0x3
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#define SFC_VER_4 0x4
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#define SFC_VER_5 0x5
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#define SFC_EN_INT (0) /* enable interrupt */
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#define SFC_EN_DMA (1) /* enable dma */
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#define SFC_FIFO_DEPTH (0x10) /* 16 words */
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/* FIFO watermark */
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#define SFC_RX_WMARK (SFC_FIFO_DEPTH) /* RX watermark level */
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#define SFC_TX_WMARK (SFC_FIFO_DEPTH) /* TX watermark level */
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#define SFC_RX_WMARK_SHIFT (8)
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#define SFC_TX_WMARK_SHIFT (0)
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/* return value */
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#define SFC_OK (0)
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#define SFC_ERROR (-1)
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#define SFC_PARAM_ERR (-2)
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#define SFC_TX_TIMEOUT (-3)
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#define SFC_RX_TIMEOUT (-4)
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#define SFC_WAIT_TIMEOUT (-5)
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#define SFC_BUSY_TIMEOUT (-6)
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#define SFC_ECC_FAIL (-7)
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#define SFC_PROG_FAIL (-8)
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#define SFC_ERASE_FAIL (-9)
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/* SFC_CMD Register */
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#define SFC_ADDR_0BITS (0)
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#define SFC_ADDR_24BITS (1)
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#define SFC_ADDR_32BITS (2)
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#define SFC_ADDR_XBITS (3)
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#define SFC_WRITE (1)
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#define SFC_READ (0)
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/* SFC_CTRL Register */
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#define SFC_1BITS_LINE (0)
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#define SFC_2BITS_LINE (1)
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#define SFC_4BITS_LINE (2)
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#define SFC_ENABLE_DMA BIT(14)
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#define sfc_delay(us) udelay(us)
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#define DMA_INT BIT(7) /* dma interrupt */
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#define NSPIERR_INT BIT(6) /* Nspi error interrupt */
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#define AHBERR_INT BIT(5) /* Ahb bus error interrupt */
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#define FINISH_INT BIT(4) /* Transfer finish interrupt */
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#define TXEMPTY_INT BIT(3) /* Tx fifo empty interrupt */
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#define TXOF_INT BIT(2) /* Tx fifo overflow interrupt */
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#define RXUF_INT BIT(1) /* Rx fifo underflow interrupt */
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#define RXFULL_INT BIT(0) /* Rx fifo full interrupt */
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/* SFC_FSR Register*/
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#define SFC_RXFULL BIT(3) /* rx fifo full */
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#define SFC_RXEMPTY BIT(2) /* rx fifo empty */
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#define SFC_TXEMPTY BIT(1) /* tx fifo empty */
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#define SFC_TXFULL BIT(0) /* tx fifo full */
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/* SFC_RCVR Register */
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#define SFC_RESET BIT(0) /* controller reset */
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/* SFC_DLL_CTRL Register */
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#define SCLK_SMP_SEL_EN BIT(15) /* SCLK Sampling Selection */
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#define SCLK_SMP_SEL_MAX_V4 0xFF /* SCLK Sampling Selection */
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#define SCLK_SMP_SEL_MAX_V5 0x1FF /* SCLK Sampling Selection */
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/* SFC_SR Register */
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/* sfc busy flag. When busy, don't try to set the control register */
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#define SFC_BUSY BIT(0)
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/* SFC_DMA_TRIGGER Register */
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/* Dma start trigger signal. Auto cleared after write */
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#define SFC_DMA_START BIT(0)
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#define SFC_CTRL 0x00
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#define SFC_IMR 0x04
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#define SFC_ICLR 0x08
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#define SFC_FTLR 0x0C
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#define SFC_RCVR 0x10
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#define SFC_AX 0x14
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#define SFC_ABIT 0x18
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#define SFC_MASKISR 0x1C
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#define SFC_FSR 0x20
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#define SFC_SR 0x24
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#define SFC_RAWISR 0x28
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#define SFC_VER 0x2C
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#define SFC_QOP 0x30
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#define SFC_DLL_CTRL0 0x3C
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#define SFC_DMA_TRIGGER 0x80
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#define SFC_DMA_ADDR 0x84
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#define SFC_LEN_CTRL 0x88
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#define SFC_LEN_EXT 0x8C
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#define SFC_CMD 0x100
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#define SFC_ADDR 0x104
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#define SFC_DATA 0x108
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union SFCFSR_DATA {
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u32 d32;
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struct {
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unsigned txempty : 1;
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unsigned txfull : 1;
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unsigned rxempty : 1;
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unsigned rxfull : 1;
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unsigned reserved7_4 : 4;
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unsigned txlevel : 5;
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unsigned reserved15_13 : 3;
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unsigned rxlevel : 5;
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unsigned reserved31_21 : 11;
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} b;
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};
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/* Manufactory ID */
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#define MID_WINBOND 0xEF
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#define MID_GIGADEV 0xC8
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#define MID_MICRON 0x2C
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#define MID_MACRONIX 0xC2
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#define MID_SPANSION 0x01
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#define MID_EON 0x1C
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#define MID_ST 0x20
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#define MID_XTX 0x0B
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#define MID_PUYA 0x85
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#define MID_XMC 0x20
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#define MID_DOSILICON 0xF8
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#define MID_ZBIT 0x5E
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/*------------------------------ Global Typedefs -----------------------------*/
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enum SFC_DATA_LINES {
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DATA_LINES_X1 = 0,
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DATA_LINES_X2,
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DATA_LINES_X4
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};
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union SFCCTRL_DATA {
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/* raw register data */
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u32 d32;
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/* register bits */
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struct {
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/* spi mode select */
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unsigned mode : 1;
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/*
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* Shift in phase selection
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* 0: shift in the flash data at posedge sclk_out
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* 1: shift in the flash data at negedge sclk_out
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*/
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unsigned sps : 1;
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unsigned reserved3_2 : 2;
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/* sclk_idle_level_cycles */
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unsigned scic : 4;
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/* Cmd bits number */
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unsigned cmdlines : 2;
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/* Address bits number */
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unsigned addrlines : 2;
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/* Data bits number */
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unsigned datalines : 2;
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/* this bit is not exit in regiseter, just use for code param */
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unsigned enbledma : 1;
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unsigned reserved15 : 1;
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unsigned addrbits : 5;
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unsigned reserved31_21 : 11;
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} b;
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};
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union SFCCMD_DATA {
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/* raw register data */
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u32 d32;
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/* register bits */
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struct {
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/* Command that will send to Serial Flash */
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unsigned cmd : 8;
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/* Dummy bits number */
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unsigned dummybits : 4;
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/* 0: read, 1: write */
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unsigned rw : 1;
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/* Continuous read mode */
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unsigned readmode : 1;
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/* Address bits number */
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unsigned addrbits : 2;
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/* Transferred bytes number */
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unsigned datasize : 14;
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/* Chip select */
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unsigned cs : 2;
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} b;
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};
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struct rk_sfc_op {
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union SFCCMD_DATA sfcmd;
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union SFCCTRL_DATA sfctrl;
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};
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#define IDB_BLOCK_TAG_ID 0xFCDC8C3B
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struct id_block_tag {
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u32 id;
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u32 version;
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u32 flags;
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u16 boot_img_offset;
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u8 reserved1[10];
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u32 dev_param[8];
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u8 reserved2[506 - 56];
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u16 data_img_len;
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u16 boot_img_len;
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u8 reserved3[512 - 510];
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} __packed;
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int sfc_init(void __iomem *reg_addr);
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int sfc_request(struct rk_sfc_op *op, u32 addr, void *data, u32 size);
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u16 sfc_get_version(void);
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void sfc_clean_irq(void);
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u32 sfc_get_max_iosize(void);
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void sfc_set_delay_lines(u16 cells);
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void sfc_disable_delay_lines(void);
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int rksfc_get_reg_addr(unsigned long *p_sfc_addr);
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#endif
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