/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __LINUX_XILINX_LL_TEMAC_H
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#define __LINUX_XILINX_LL_TEMAC_H
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#include <linux/if_ether.h>
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#include <linux/phy.h>
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#include <linux/spinlock.h>
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struct ll_temac_platform_data {
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bool txcsum; /* Enable/disable TX checksum */
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bool rxcsum; /* Enable/disable RX checksum */
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u8 mac_addr[ETH_ALEN]; /* MAC address (6 bytes) */
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/* Clock frequency for input to MDIO clock generator */
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u32 mdio_clk_freq;
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unsigned long long mdio_bus_id; /* Unique id for MDIO bus */
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int phy_addr; /* Address of the PHY to connect to */
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phy_interface_t phy_interface; /* PHY interface mode */
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bool reg_little_endian; /* Little endian TEMAC register access */
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bool dma_little_endian; /* Little endian DMA register access */
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/* Pre-initialized mutex to use for synchronizing indirect
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* register access. When using both interfaces of a single
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* TEMAC IP block, the same mutex should be passed here, as
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* they share the same DCR bus bridge.
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*/
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spinlock_t *indirect_lock;
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/* DMA channel control setup */
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u8 tx_irq_timeout; /* TX Interrupt Delay Time-out */
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u8 tx_irq_count; /* TX Interrupt Coalescing Threshold Count */
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u8 rx_irq_timeout; /* RX Interrupt Delay Time-out */
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u8 rx_irq_count; /* RX Interrupt Coalescing Threshold Count */
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};
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#endif /* __LINUX_XILINX_LL_TEMAC_H */
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