/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Core interface for Intel MSIC
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*
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* Copyright (C) 2011, Intel Corporation
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* Author: Mika Westerberg <mika.westerberg@linux.intel.com>
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*/
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#ifndef __LINUX_MFD_INTEL_MSIC_H__
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#define __LINUX_MFD_INTEL_MSIC_H__
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/* ID */
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#define INTEL_MSIC_ID0 0x000 /* RO */
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#define INTEL_MSIC_ID1 0x001 /* RO */
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/* IRQ */
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#define INTEL_MSIC_IRQLVL1 0x002
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#define INTEL_MSIC_ADC1INT 0x003
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#define INTEL_MSIC_CCINT 0x004
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#define INTEL_MSIC_PWRSRCINT 0x005
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#define INTEL_MSIC_PWRSRCINT1 0x006
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#define INTEL_MSIC_CHRINT 0x007
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#define INTEL_MSIC_CHRINT1 0x008
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#define INTEL_MSIC_RTCIRQ 0x009
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#define INTEL_MSIC_GPIO0LVIRQ 0x00a
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#define INTEL_MSIC_GPIO1LVIRQ 0x00b
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#define INTEL_MSIC_GPIOHVIRQ 0x00c
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#define INTEL_MSIC_VRINT 0x00d
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#define INTEL_MSIC_OCAUDIO 0x00e
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#define INTEL_MSIC_ACCDET 0x00f
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#define INTEL_MSIC_RESETIRQ1 0x010
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#define INTEL_MSIC_RESETIRQ2 0x011
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#define INTEL_MSIC_MADC1INT 0x012
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#define INTEL_MSIC_MCCINT 0x013
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#define INTEL_MSIC_MPWRSRCINT 0x014
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#define INTEL_MSIC_MPWRSRCINT1 0x015
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#define INTEL_MSIC_MCHRINT 0x016
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#define INTEL_MSIC_MCHRINT1 0x017
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#define INTEL_MSIC_RTCIRQMASK 0x018
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#define INTEL_MSIC_GPIO0LVIRQMASK 0x019
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#define INTEL_MSIC_GPIO1LVIRQMASK 0x01a
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#define INTEL_MSIC_GPIOHVIRQMASK 0x01b
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#define INTEL_MSIC_VRINTMASK 0x01c
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#define INTEL_MSIC_OCAUDIOMASK 0x01d
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#define INTEL_MSIC_ACCDETMASK 0x01e
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#define INTEL_MSIC_RESETIRQ1MASK 0x01f
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#define INTEL_MSIC_RESETIRQ2MASK 0x020
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#define INTEL_MSIC_IRQLVL1MSK 0x021
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#define INTEL_MSIC_PBCONFIG 0x03e
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#define INTEL_MSIC_PBSTATUS 0x03f /* RO */
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/* GPIO */
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#define INTEL_MSIC_GPIO0LV7CTLO 0x040
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#define INTEL_MSIC_GPIO0LV6CTLO 0x041
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#define INTEL_MSIC_GPIO0LV5CTLO 0x042
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#define INTEL_MSIC_GPIO0LV4CTLO 0x043
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#define INTEL_MSIC_GPIO0LV3CTLO 0x044
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#define INTEL_MSIC_GPIO0LV2CTLO 0x045
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#define INTEL_MSIC_GPIO0LV1CTLO 0x046
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#define INTEL_MSIC_GPIO0LV0CTLO 0x047
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#define INTEL_MSIC_GPIO1LV7CTLOS 0x048
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#define INTEL_MSIC_GPIO1LV6CTLO 0x049
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#define INTEL_MSIC_GPIO1LV5CTLO 0x04a
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#define INTEL_MSIC_GPIO1LV4CTLO 0x04b
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#define INTEL_MSIC_GPIO1LV3CTLO 0x04c
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#define INTEL_MSIC_GPIO1LV2CTLO 0x04d
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#define INTEL_MSIC_GPIO1LV1CTLO 0x04e
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#define INTEL_MSIC_GPIO1LV0CTLO 0x04f
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#define INTEL_MSIC_GPIO0LV7CTLI 0x050
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#define INTEL_MSIC_GPIO0LV6CTLI 0x051
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#define INTEL_MSIC_GPIO0LV5CTLI 0x052
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#define INTEL_MSIC_GPIO0LV4CTLI 0x053
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#define INTEL_MSIC_GPIO0LV3CTLI 0x054
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#define INTEL_MSIC_GPIO0LV2CTLI 0x055
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#define INTEL_MSIC_GPIO0LV1CTLI 0x056
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#define INTEL_MSIC_GPIO0LV0CTLI 0x057
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#define INTEL_MSIC_GPIO1LV7CTLIS 0x058
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#define INTEL_MSIC_GPIO1LV6CTLI 0x059
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#define INTEL_MSIC_GPIO1LV5CTLI 0x05a
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#define INTEL_MSIC_GPIO1LV4CTLI 0x05b
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#define INTEL_MSIC_GPIO1LV3CTLI 0x05c
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#define INTEL_MSIC_GPIO1LV2CTLI 0x05d
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#define INTEL_MSIC_GPIO1LV1CTLI 0x05e
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#define INTEL_MSIC_GPIO1LV0CTLI 0x05f
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#define INTEL_MSIC_PWM0CLKDIV1 0x061
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#define INTEL_MSIC_PWM0CLKDIV0 0x062
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#define INTEL_MSIC_PWM1CLKDIV1 0x063
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#define INTEL_MSIC_PWM1CLKDIV0 0x064
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#define INTEL_MSIC_PWM2CLKDIV1 0x065
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#define INTEL_MSIC_PWM2CLKDIV0 0x066
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#define INTEL_MSIC_PWM0DUTYCYCLE 0x067
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#define INTEL_MSIC_PWM1DUTYCYCLE 0x068
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#define INTEL_MSIC_PWM2DUTYCYCLE 0x069
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#define INTEL_MSIC_GPIO0HV3CTLO 0x06d
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#define INTEL_MSIC_GPIO0HV2CTLO 0x06e
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#define INTEL_MSIC_GPIO0HV1CTLO 0x06f
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#define INTEL_MSIC_GPIO0HV0CTLO 0x070
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#define INTEL_MSIC_GPIO1HV3CTLO 0x071
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#define INTEL_MSIC_GPIO1HV2CTLO 0x072
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#define INTEL_MSIC_GPIO1HV1CTLO 0x073
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#define INTEL_MSIC_GPIO1HV0CTLO 0x074
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#define INTEL_MSIC_GPIO0HV3CTLI 0x075
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#define INTEL_MSIC_GPIO0HV2CTLI 0x076
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#define INTEL_MSIC_GPIO0HV1CTLI 0x077
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#define INTEL_MSIC_GPIO0HV0CTLI 0x078
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#define INTEL_MSIC_GPIO1HV3CTLI 0x079
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#define INTEL_MSIC_GPIO1HV2CTLI 0x07a
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#define INTEL_MSIC_GPIO1HV1CTLI 0x07b
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#define INTEL_MSIC_GPIO1HV0CTLI 0x07c
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/* SVID */
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#define INTEL_MSIC_SVIDCTRL0 0x080
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#define INTEL_MSIC_SVIDCTRL1 0x081
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#define INTEL_MSIC_SVIDCTRL2 0x082
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#define INTEL_MSIC_SVIDTXLASTPKT3 0x083 /* RO */
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#define INTEL_MSIC_SVIDTXLASTPKT2 0x084 /* RO */
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#define INTEL_MSIC_SVIDTXLASTPKT1 0x085 /* RO */
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#define INTEL_MSIC_SVIDTXLASTPKT0 0x086 /* RO */
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#define INTEL_MSIC_SVIDPKTOUTBYTE3 0x087
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#define INTEL_MSIC_SVIDPKTOUTBYTE2 0x088
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#define INTEL_MSIC_SVIDPKTOUTBYTE1 0x089
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#define INTEL_MSIC_SVIDPKTOUTBYTE0 0x08a
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#define INTEL_MSIC_SVIDRXVPDEBUG1 0x08b
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#define INTEL_MSIC_SVIDRXVPDEBUG0 0x08c
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#define INTEL_MSIC_SVIDRXLASTPKT3 0x08d /* RO */
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#define INTEL_MSIC_SVIDRXLASTPKT2 0x08e /* RO */
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#define INTEL_MSIC_SVIDRXLASTPKT1 0x08f /* RO */
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#define INTEL_MSIC_SVIDRXLASTPKT0 0x090 /* RO */
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#define INTEL_MSIC_SVIDRXCHKSTATUS3 0x091 /* RO */
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#define INTEL_MSIC_SVIDRXCHKSTATUS2 0x092 /* RO */
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#define INTEL_MSIC_SVIDRXCHKSTATUS1 0x093 /* RO */
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#define INTEL_MSIC_SVIDRXCHKSTATUS0 0x094 /* RO */
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/* VREG */
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#define INTEL_MSIC_VCCLATCH 0x0c0
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#define INTEL_MSIC_VNNLATCH 0x0c1
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#define INTEL_MSIC_VCCCNT 0x0c2
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#define INTEL_MSIC_SMPSRAMP 0x0c3
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#define INTEL_MSIC_VNNCNT 0x0c4
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#define INTEL_MSIC_VNNAONCNT 0x0c5
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#define INTEL_MSIC_VCC122AONCNT 0x0c6
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#define INTEL_MSIC_V180AONCNT 0x0c7
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#define INTEL_MSIC_V500CNT 0x0c8
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#define INTEL_MSIC_VIHFCNT 0x0c9
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#define INTEL_MSIC_LDORAMP1 0x0ca
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#define INTEL_MSIC_LDORAMP2 0x0cb
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#define INTEL_MSIC_VCC108AONCNT 0x0cc
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#define INTEL_MSIC_VCC108ASCNT 0x0cd
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#define INTEL_MSIC_VCC108CNT 0x0ce
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#define INTEL_MSIC_VCCA100ASCNT 0x0cf
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#define INTEL_MSIC_VCCA100CNT 0x0d0
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#define INTEL_MSIC_VCC180AONCNT 0x0d1
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#define INTEL_MSIC_VCC180CNT 0x0d2
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#define INTEL_MSIC_VCC330CNT 0x0d3
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#define INTEL_MSIC_VUSB330CNT 0x0d4
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#define INTEL_MSIC_VCCSDIOCNT 0x0d5
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#define INTEL_MSIC_VPROG1CNT 0x0d6
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#define INTEL_MSIC_VPROG2CNT 0x0d7
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#define INTEL_MSIC_VEMMCSCNT 0x0d8
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#define INTEL_MSIC_VEMMC1CNT 0x0d9
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#define INTEL_MSIC_VEMMC2CNT 0x0da
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#define INTEL_MSIC_VAUDACNT 0x0db
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#define INTEL_MSIC_VHSPCNT 0x0dc
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#define INTEL_MSIC_VHSNCNT 0x0dd
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#define INTEL_MSIC_VHDMICNT 0x0de
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#define INTEL_MSIC_VOTGCNT 0x0df
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#define INTEL_MSIC_V1P35CNT 0x0e0
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#define INTEL_MSIC_V330AONCNT 0x0e1
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/* RESET */
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#define INTEL_MSIC_CHIPCNTRL 0x100 /* WO */
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#define INTEL_MSIC_ERCONFIG 0x101
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/* BURST */
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#define INTEL_MSIC_BATCURRENTLIMIT12 0x102
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#define INTEL_MSIC_BATTIMELIMIT12 0x103
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#define INTEL_MSIC_BATTIMELIMIT3 0x104
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#define INTEL_MSIC_BATTIMEDB 0x105
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#define INTEL_MSIC_BRSTCONFIGOUTPUTS 0x106
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#define INTEL_MSIC_BRSTCONFIGACTIONS 0x107
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#define INTEL_MSIC_BURSTCONTROLSTATUS 0x108
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/* RTC */
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#define INTEL_MSIC_RTCB1 0x140 /* RO */
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#define INTEL_MSIC_RTCB2 0x141 /* RO */
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#define INTEL_MSIC_RTCB3 0x142 /* RO */
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#define INTEL_MSIC_RTCB4 0x143 /* RO */
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#define INTEL_MSIC_RTCOB1 0x144
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#define INTEL_MSIC_RTCOB2 0x145
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#define INTEL_MSIC_RTCOB3 0x146
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#define INTEL_MSIC_RTCOB4 0x147
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#define INTEL_MSIC_RTCAB1 0x148
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#define INTEL_MSIC_RTCAB2 0x149
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#define INTEL_MSIC_RTCAB3 0x14a
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#define INTEL_MSIC_RTCAB4 0x14b
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#define INTEL_MSIC_RTCWAB1 0x14c
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#define INTEL_MSIC_RTCWAB2 0x14d
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#define INTEL_MSIC_RTCWAB3 0x14e
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#define INTEL_MSIC_RTCWAB4 0x14f
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#define INTEL_MSIC_RTCSC1 0x150
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#define INTEL_MSIC_RTCSC2 0x151
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#define INTEL_MSIC_RTCSC3 0x152
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#define INTEL_MSIC_RTCSC4 0x153
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#define INTEL_MSIC_RTCSTATUS 0x154 /* RO */
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#define INTEL_MSIC_RTCCONFIG1 0x155
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#define INTEL_MSIC_RTCCONFIG2 0x156
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/* CHARGER */
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#define INTEL_MSIC_BDTIMER 0x180
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#define INTEL_MSIC_BATTRMV 0x181
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#define INTEL_MSIC_VBUSDET 0x182
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#define INTEL_MSIC_VBUSDET1 0x183
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#define INTEL_MSIC_ADPHVDET 0x184
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#define INTEL_MSIC_ADPLVDET 0x185
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#define INTEL_MSIC_ADPDETDBDM 0x186
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#define INTEL_MSIC_LOWBATTDET 0x187
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#define INTEL_MSIC_CHRCTRL 0x188
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#define INTEL_MSIC_CHRCVOLTAGE 0x189
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#define INTEL_MSIC_CHRCCURRENT 0x18a
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#define INTEL_MSIC_SPCHARGER 0x18b
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#define INTEL_MSIC_CHRTTIME 0x18c
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#define INTEL_MSIC_CHRCTRL1 0x18d
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#define INTEL_MSIC_PWRSRCLMT 0x18e
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#define INTEL_MSIC_CHRSTWDT 0x18f
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#define INTEL_MSIC_WDTWRITE 0x190 /* WO */
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#define INTEL_MSIC_CHRSAFELMT 0x191
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#define INTEL_MSIC_SPWRSRCINT 0x192 /* RO */
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#define INTEL_MSIC_SPWRSRCINT1 0x193 /* RO */
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#define INTEL_MSIC_CHRLEDPWM 0x194
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#define INTEL_MSIC_CHRLEDCTRL 0x195
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/* ADC */
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#define INTEL_MSIC_ADC1CNTL1 0x1c0
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#define INTEL_MSIC_ADC1CNTL2 0x1c1
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#define INTEL_MSIC_ADC1CNTL3 0x1c2
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#define INTEL_MSIC_ADC1OFFSETH 0x1c3 /* RO */
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#define INTEL_MSIC_ADC1OFFSETL 0x1c4 /* RO */
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#define INTEL_MSIC_ADC1ADDR0 0x1c5
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#define INTEL_MSIC_ADC1ADDR1 0x1c6
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#define INTEL_MSIC_ADC1ADDR2 0x1c7
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#define INTEL_MSIC_ADC1ADDR3 0x1c8
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#define INTEL_MSIC_ADC1ADDR4 0x1c9
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#define INTEL_MSIC_ADC1ADDR5 0x1ca
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#define INTEL_MSIC_ADC1ADDR6 0x1cb
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#define INTEL_MSIC_ADC1ADDR7 0x1cc
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#define INTEL_MSIC_ADC1ADDR8 0x1cd
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#define INTEL_MSIC_ADC1ADDR9 0x1ce
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#define INTEL_MSIC_ADC1ADDR10 0x1cf
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#define INTEL_MSIC_ADC1ADDR11 0x1d0
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#define INTEL_MSIC_ADC1ADDR12 0x1d1
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#define INTEL_MSIC_ADC1ADDR13 0x1d2
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#define INTEL_MSIC_ADC1ADDR14 0x1d3
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#define INTEL_MSIC_ADC1SNS0H 0x1d4 /* RO */
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#define INTEL_MSIC_ADC1SNS0L 0x1d5 /* RO */
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#define INTEL_MSIC_ADC1SNS1H 0x1d6 /* RO */
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#define INTEL_MSIC_ADC1SNS1L 0x1d7 /* RO */
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#define INTEL_MSIC_ADC1SNS2H 0x1d8 /* RO */
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#define INTEL_MSIC_ADC1SNS2L 0x1d9 /* RO */
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#define INTEL_MSIC_ADC1SNS3H 0x1da /* RO */
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#define INTEL_MSIC_ADC1SNS3L 0x1db /* RO */
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#define INTEL_MSIC_ADC1SNS4H 0x1dc /* RO */
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#define INTEL_MSIC_ADC1SNS4L 0x1dd /* RO */
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#define INTEL_MSIC_ADC1SNS5H 0x1de /* RO */
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#define INTEL_MSIC_ADC1SNS5L 0x1df /* RO */
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#define INTEL_MSIC_ADC1SNS6H 0x1e0 /* RO */
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#define INTEL_MSIC_ADC1SNS6L 0x1e1 /* RO */
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#define INTEL_MSIC_ADC1SNS7H 0x1e2 /* RO */
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#define INTEL_MSIC_ADC1SNS7L 0x1e3 /* RO */
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#define INTEL_MSIC_ADC1SNS8H 0x1e4 /* RO */
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#define INTEL_MSIC_ADC1SNS8L 0x1e5 /* RO */
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#define INTEL_MSIC_ADC1SNS9H 0x1e6 /* RO */
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#define INTEL_MSIC_ADC1SNS9L 0x1e7 /* RO */
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#define INTEL_MSIC_ADC1SNS10H 0x1e8 /* RO */
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#define INTEL_MSIC_ADC1SNS10L 0x1e9 /* RO */
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#define INTEL_MSIC_ADC1SNS11H 0x1ea /* RO */
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#define INTEL_MSIC_ADC1SNS11L 0x1eb /* RO */
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#define INTEL_MSIC_ADC1SNS12H 0x1ec /* RO */
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#define INTEL_MSIC_ADC1SNS12L 0x1ed /* RO */
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#define INTEL_MSIC_ADC1SNS13H 0x1ee /* RO */
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#define INTEL_MSIC_ADC1SNS13L 0x1ef /* RO */
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#define INTEL_MSIC_ADC1SNS14H 0x1f0 /* RO */
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#define INTEL_MSIC_ADC1SNS14L 0x1f1 /* RO */
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#define INTEL_MSIC_ADC1BV0H 0x1f2 /* RO */
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#define INTEL_MSIC_ADC1BV0L 0x1f3 /* RO */
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#define INTEL_MSIC_ADC1BV1H 0x1f4 /* RO */
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#define INTEL_MSIC_ADC1BV1L 0x1f5 /* RO */
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#define INTEL_MSIC_ADC1BV2H 0x1f6 /* RO */
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#define INTEL_MSIC_ADC1BV2L 0x1f7 /* RO */
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#define INTEL_MSIC_ADC1BV3H 0x1f8 /* RO */
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#define INTEL_MSIC_ADC1BV3L 0x1f9 /* RO */
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#define INTEL_MSIC_ADC1BI0H 0x1fa /* RO */
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#define INTEL_MSIC_ADC1BI0L 0x1fb /* RO */
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#define INTEL_MSIC_ADC1BI1H 0x1fc /* RO */
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#define INTEL_MSIC_ADC1BI1L 0x1fd /* RO */
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#define INTEL_MSIC_ADC1BI2H 0x1fe /* RO */
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#define INTEL_MSIC_ADC1BI2L 0x1ff /* RO */
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#define INTEL_MSIC_ADC1BI3H 0x200 /* RO */
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#define INTEL_MSIC_ADC1BI3L 0x201 /* RO */
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#define INTEL_MSIC_CCCNTL 0x202
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#define INTEL_MSIC_CCOFFSETH 0x203 /* RO */
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#define INTEL_MSIC_CCOFFSETL 0x204 /* RO */
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#define INTEL_MSIC_CCADCHA 0x205 /* RO */
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#define INTEL_MSIC_CCADCLA 0x206 /* RO */
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/* AUDIO */
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#define INTEL_MSIC_AUDPLLCTRL 0x240
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#define INTEL_MSIC_DMICBUF0123 0x241
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#define INTEL_MSIC_DMICBUF45 0x242
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#define INTEL_MSIC_DMICGPO 0x244
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#define INTEL_MSIC_DMICMUX 0x245
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#define INTEL_MSIC_DMICCLK 0x246
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#define INTEL_MSIC_MICBIAS 0x247
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#define INTEL_MSIC_ADCCONFIG 0x248
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#define INTEL_MSIC_MICAMP1 0x249
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#define INTEL_MSIC_MICAMP2 0x24a
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#define INTEL_MSIC_NOISEMUX 0x24b
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#define INTEL_MSIC_AUDIOMUX12 0x24c
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#define INTEL_MSIC_AUDIOMUX34 0x24d
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#define INTEL_MSIC_AUDIOSINC 0x24e
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#define INTEL_MSIC_AUDIOTXEN 0x24f
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#define INTEL_MSIC_HSEPRXCTRL 0x250
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#define INTEL_MSIC_IHFRXCTRL 0x251
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#define INTEL_MSIC_VOICETXVOL 0x252
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#define INTEL_MSIC_SIDETONEVOL 0x253
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#define INTEL_MSIC_MUSICSHARVOL 0x254
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#define INTEL_MSIC_VOICETXCTRL 0x255
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#define INTEL_MSIC_HSMIXER 0x256
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#define INTEL_MSIC_DACCONFIG 0x257
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#define INTEL_MSIC_SOFTMUTE 0x258
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#define INTEL_MSIC_HSLVOLCTRL 0x259
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#define INTEL_MSIC_HSRVOLCTRL 0x25a
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#define INTEL_MSIC_IHFLVOLCTRL 0x25b
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#define INTEL_MSIC_IHFRVOLCTRL 0x25c
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#define INTEL_MSIC_DRIVEREN 0x25d
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#define INTEL_MSIC_LINEOUTCTRL 0x25e
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#define INTEL_MSIC_VIB1CTRL1 0x25f
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#define INTEL_MSIC_VIB1CTRL2 0x260
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#define INTEL_MSIC_VIB1CTRL3 0x261
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#define INTEL_MSIC_VIB1SPIPCM_1 0x262
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#define INTEL_MSIC_VIB1SPIPCM_2 0x263
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#define INTEL_MSIC_VIB1CTRL5 0x264
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#define INTEL_MSIC_VIB2CTRL1 0x265
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#define INTEL_MSIC_VIB2CTRL2 0x266
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#define INTEL_MSIC_VIB2CTRL3 0x267
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#define INTEL_MSIC_VIB2SPIPCM_1 0x268
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#define INTEL_MSIC_VIB2SPIPCM_2 0x269
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#define INTEL_MSIC_VIB2CTRL5 0x26a
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#define INTEL_MSIC_BTNCTRL1 0x26b
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#define INTEL_MSIC_BTNCTRL2 0x26c
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#define INTEL_MSIC_PCM1TXSLOT01 0x26d
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#define INTEL_MSIC_PCM1TXSLOT23 0x26e
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#define INTEL_MSIC_PCM1TXSLOT45 0x26f
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#define INTEL_MSIC_PCM1RXSLOT0123 0x270
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#define INTEL_MSIC_PCM1RXSLOT045 0x271
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#define INTEL_MSIC_PCM2TXSLOT01 0x272
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#define INTEL_MSIC_PCM2TXSLOT23 0x273
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#define INTEL_MSIC_PCM2TXSLOT45 0x274
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#define INTEL_MSIC_PCM2RXSLOT01 0x275
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#define INTEL_MSIC_PCM2RXSLOT23 0x276
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#define INTEL_MSIC_PCM2RXSLOT45 0x277
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#define INTEL_MSIC_PCM1CTRL1 0x278
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#define INTEL_MSIC_PCM1CTRL2 0x279
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#define INTEL_MSIC_PCM1CTRL3 0x27a
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#define INTEL_MSIC_PCM2CTRL1 0x27b
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#define INTEL_MSIC_PCM2CTRL2 0x27c
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/* HDMI */
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#define INTEL_MSIC_HDMIPUEN 0x280
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#define INTEL_MSIC_HDMISTATUS 0x281 /* RO */
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/* Physical address of the start of the MSIC interrupt tree in SRAM */
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#define INTEL_MSIC_IRQ_PHYS_BASE 0xffff7fc0
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/**
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* struct intel_msic_gpio_pdata - platform data for the MSIC GPIO driver
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* @gpio_base: base number for the GPIOs
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*/
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struct intel_msic_gpio_pdata {
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unsigned gpio_base;
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};
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/**
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* struct intel_msic_ocd_pdata - platform data for the MSIC OCD driver
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* @gpio: GPIO number used for OCD interrupts
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*
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* The MSIC MFD driver converts @gpio into an IRQ number and passes it to
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* the OCD driver as %IORESOURCE_IRQ.
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*/
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struct intel_msic_ocd_pdata {
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unsigned gpio;
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};
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/* MSIC embedded blocks (subdevices) */
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enum intel_msic_block {
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INTEL_MSIC_BLOCK_TOUCH,
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INTEL_MSIC_BLOCK_ADC,
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INTEL_MSIC_BLOCK_BATTERY,
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INTEL_MSIC_BLOCK_GPIO,
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INTEL_MSIC_BLOCK_AUDIO,
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INTEL_MSIC_BLOCK_HDMI,
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INTEL_MSIC_BLOCK_THERMAL,
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INTEL_MSIC_BLOCK_POWER_BTN,
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INTEL_MSIC_BLOCK_OCD,
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INTEL_MSIC_BLOCK_LAST,
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};
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/**
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* struct intel_msic_platform_data - platform data for the MSIC driver
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* @irq: array of interrupt numbers, one per device. If @irq is set to %0
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* for a given block, the corresponding platform device is not
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* created. For devices which don't have an interrupt, use %0xff
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* (this is same as in SFI spec).
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* @gpio: platform data for the MSIC GPIO driver
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* @ocd: platform data for the MSIC OCD driver
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*
|
* Once the MSIC driver is initialized, the register interface is ready to
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* use. All the platform devices for subdevices are created after the
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* register interface is ready so that we can guarantee its availability to
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* the subdevice drivers.
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*
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* Interrupt numbers are passed to the subdevices via %IORESOURCE_IRQ
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* resources of the created platform device.
|
*/
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struct intel_msic_platform_data {
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int irq[INTEL_MSIC_BLOCK_LAST];
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struct intel_msic_gpio_pdata *gpio;
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struct intel_msic_ocd_pdata *ocd;
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};
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|
struct intel_msic;
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extern int intel_msic_reg_read(unsigned short reg, u8 *val);
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extern int intel_msic_reg_write(unsigned short reg, u8 val);
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extern int intel_msic_reg_update(unsigned short reg, u8 val, u8 mask);
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extern int intel_msic_bulk_read(unsigned short *reg, u8 *buf, size_t count);
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extern int intel_msic_bulk_write(unsigned short *reg, u8 *buf, size_t count);
|
|
/*
|
* pdev_to_intel_msic - gets an MSIC instance from the platform device
|
* @pdev: platform device pointer
|
*
|
* The client drivers need to have pointer to the MSIC instance if they
|
* want to call intel_msic_irq_read(). This macro can be used for
|
* convenience to get the MSIC pointer from @pdev where needed. This is
|
* _only_ valid for devices which are managed by the MSIC.
|
*/
|
#define pdev_to_intel_msic(pdev) (dev_get_drvdata(pdev->dev.parent))
|
|
extern int intel_msic_irq_read(struct intel_msic *msic, unsigned short reg,
|
u8 *val);
|
|
#endif /* __LINUX_MFD_INTEL_MSIC_H__ */
|
