/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright 2009 Daniel Ribeiro <drwyrm@gmail.com>
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*
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* For further information, please see http://wiki.openezx.org/PCAP2
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*/
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#ifndef EZX_PCAP_H
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#define EZX_PCAP_H
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struct pcap_subdev {
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int id;
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const char *name;
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void *platform_data;
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};
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struct pcap_platform_data {
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unsigned int irq_base;
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unsigned int config;
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int gpio;
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void (*init) (void *); /* board specific init */
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int num_subdevs;
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struct pcap_subdev *subdevs;
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};
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struct pcap_chip;
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int ezx_pcap_write(struct pcap_chip *, u8, u32);
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int ezx_pcap_read(struct pcap_chip *, u8, u32 *);
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int ezx_pcap_set_bits(struct pcap_chip *, u8, u32, u32);
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int pcap_to_irq(struct pcap_chip *, int);
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int irq_to_pcap(struct pcap_chip *, int);
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int pcap_adc_async(struct pcap_chip *, u8, u32, u8[], void *, void *);
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int pcap_adc_sync(struct pcap_chip *, u8, u32, u8[], u16[]);
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void pcap_set_ts_bits(struct pcap_chip *, u32);
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#define PCAP_SECOND_PORT 1
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#define PCAP_CS_AH 2
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#define PCAP_REGISTER_WRITE_OP_BIT 0x80000000
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#define PCAP_REGISTER_READ_OP_BIT 0x00000000
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#define PCAP_REGISTER_VALUE_MASK 0x01ffffff
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#define PCAP_REGISTER_ADDRESS_MASK 0x7c000000
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#define PCAP_REGISTER_ADDRESS_SHIFT 26
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#define PCAP_REGISTER_NUMBER 32
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#define PCAP_CLEAR_INTERRUPT_REGISTER 0x01ffffff
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#define PCAP_MASK_ALL_INTERRUPT 0x01ffffff
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/* registers accessible by both pcap ports */
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#define PCAP_REG_ISR 0x0 /* Interrupt Status */
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#define PCAP_REG_MSR 0x1 /* Interrupt Mask */
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#define PCAP_REG_PSTAT 0x2 /* Processor Status */
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#define PCAP_REG_VREG2 0x6 /* Regulator Bank 2 Control */
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#define PCAP_REG_AUXVREG 0x7 /* Auxiliary Regulator Control */
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#define PCAP_REG_BATT 0x8 /* Battery Control */
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#define PCAP_REG_ADC 0x9 /* AD Control */
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#define PCAP_REG_ADR 0xa /* AD Result */
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#define PCAP_REG_CODEC 0xb /* Audio Codec Control */
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#define PCAP_REG_RX_AMPS 0xc /* RX Audio Amplifiers Control */
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#define PCAP_REG_ST_DAC 0xd /* Stereo DAC Control */
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#define PCAP_REG_BUSCTRL 0x14 /* Connectivity Control */
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#define PCAP_REG_PERIPH 0x15 /* Peripheral Control */
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#define PCAP_REG_LOWPWR 0x18 /* Regulator Low Power Control */
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#define PCAP_REG_TX_AMPS 0x1a /* TX Audio Amplifiers Control */
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#define PCAP_REG_GP 0x1b /* General Purpose */
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#define PCAP_REG_TEST1 0x1c
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#define PCAP_REG_TEST2 0x1d
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#define PCAP_REG_VENDOR_TEST1 0x1e
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#define PCAP_REG_VENDOR_TEST2 0x1f
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/* registers accessible by pcap port 1 only (a1200, e2 & e6) */
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#define PCAP_REG_INT_SEL 0x3 /* Interrupt Select */
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#define PCAP_REG_SWCTRL 0x4 /* Switching Regulator Control */
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#define PCAP_REG_VREG1 0x5 /* Regulator Bank 1 Control */
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#define PCAP_REG_RTC_TOD 0xe /* RTC Time of Day */
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#define PCAP_REG_RTC_TODA 0xf /* RTC Time of Day Alarm */
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#define PCAP_REG_RTC_DAY 0x10 /* RTC Day */
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#define PCAP_REG_RTC_DAYA 0x11 /* RTC Day Alarm */
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#define PCAP_REG_MTRTMR 0x12 /* AD Monitor Timer */
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#define PCAP_REG_PWR 0x13 /* Power Control */
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#define PCAP_REG_AUXVREG_MASK 0x16 /* Auxiliary Regulator Mask */
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#define PCAP_REG_VENDOR_REV 0x17
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#define PCAP_REG_PERIPH_MASK 0x19 /* Peripheral Mask */
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/* PCAP2 Interrupts */
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#define PCAP_NIRQS 23
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#define PCAP_IRQ_ADCDONE 0 /* ADC done port 1 */
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#define PCAP_IRQ_TS 1 /* Touch Screen */
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#define PCAP_IRQ_1HZ 2 /* 1HZ timer */
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#define PCAP_IRQ_WH 3 /* ADC above high limit */
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#define PCAP_IRQ_WL 4 /* ADC below low limit */
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#define PCAP_IRQ_TODA 5 /* Time of day alarm */
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#define PCAP_IRQ_USB4V 6 /* USB above 4V */
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#define PCAP_IRQ_ONOFF 7 /* On/Off button */
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#define PCAP_IRQ_ONOFF2 8 /* On/Off button 2 */
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#define PCAP_IRQ_USB1V 9 /* USB above 1V */
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#define PCAP_IRQ_MOBPORT 10
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#define PCAP_IRQ_MIC 11 /* Mic attach/HS button */
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#define PCAP_IRQ_HS 12 /* Headset attach */
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#define PCAP_IRQ_ST 13
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#define PCAP_IRQ_PC 14 /* Power Cut */
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#define PCAP_IRQ_WARM 15
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#define PCAP_IRQ_EOL 16 /* Battery End Of Life */
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#define PCAP_IRQ_CLK 17
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#define PCAP_IRQ_SYSRST 18 /* System Reset */
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#define PCAP_IRQ_DUMMY 19
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#define PCAP_IRQ_ADCDONE2 20 /* ADC done port 2 */
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#define PCAP_IRQ_SOFTRESET 21
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#define PCAP_IRQ_MNEXB 22
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/* voltage regulators */
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#define V1 0
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#define V2 1
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#define V3 2
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#define V4 3
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#define V5 4
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#define V6 5
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#define V7 6
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#define V8 7
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#define V9 8
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#define V10 9
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#define VAUX1 10
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#define VAUX2 11
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#define VAUX3 12
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#define VAUX4 13
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#define VSIM 14
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#define VSIM2 15
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#define VVIB 16
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#define SW1 17
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#define SW2 18
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#define SW3 19
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#define SW1S 20
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#define SW2S 21
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#define PCAP_BATT_DAC_MASK 0x000000ff
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#define PCAP_BATT_DAC_SHIFT 0
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#define PCAP_BATT_B_FDBK (1 << 8)
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#define PCAP_BATT_EXT_ISENSE (1 << 9)
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#define PCAP_BATT_V_COIN_MASK 0x00003c00
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#define PCAP_BATT_V_COIN_SHIFT 10
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#define PCAP_BATT_I_COIN (1 << 14)
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#define PCAP_BATT_COIN_CH_EN (1 << 15)
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#define PCAP_BATT_EOL_SEL_MASK 0x000e0000
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#define PCAP_BATT_EOL_SEL_SHIFT 17
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#define PCAP_BATT_EOL_CMP_EN (1 << 20)
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#define PCAP_BATT_BATT_DET_EN (1 << 21)
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#define PCAP_BATT_THERMBIAS_CTRL (1 << 22)
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#define PCAP_ADC_ADEN (1 << 0)
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#define PCAP_ADC_RAND (1 << 1)
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#define PCAP_ADC_AD_SEL1 (1 << 2)
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#define PCAP_ADC_AD_SEL2 (1 << 3)
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#define PCAP_ADC_ADA1_MASK 0x00000070
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#define PCAP_ADC_ADA1_SHIFT 4
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#define PCAP_ADC_ADA2_MASK 0x00000380
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#define PCAP_ADC_ADA2_SHIFT 7
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#define PCAP_ADC_ATO_MASK 0x00003c00
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#define PCAP_ADC_ATO_SHIFT 10
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#define PCAP_ADC_ATOX (1 << 14)
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#define PCAP_ADC_MTR1 (1 << 15)
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#define PCAP_ADC_MTR2 (1 << 16)
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#define PCAP_ADC_TS_M_MASK 0x000e0000
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#define PCAP_ADC_TS_M_SHIFT 17
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#define PCAP_ADC_TS_REF_LOWPWR (1 << 20)
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#define PCAP_ADC_TS_REFENB (1 << 21)
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#define PCAP_ADC_BATT_I_POLARITY (1 << 22)
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#define PCAP_ADC_BATT_I_ADC (1 << 23)
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#define PCAP_ADC_BANK_0 0
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#define PCAP_ADC_BANK_1 1
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/* ADC bank 0 */
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#define PCAP_ADC_CH_COIN 0
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#define PCAP_ADC_CH_BATT 1
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#define PCAP_ADC_CH_BPLUS 2
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#define PCAP_ADC_CH_MOBPORTB 3
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#define PCAP_ADC_CH_TEMPERATURE 4
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#define PCAP_ADC_CH_CHARGER_ID 5
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#define PCAP_ADC_CH_AD6 6
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/* ADC bank 1 */
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#define PCAP_ADC_CH_AD7 0
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#define PCAP_ADC_CH_AD8 1
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#define PCAP_ADC_CH_AD9 2
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#define PCAP_ADC_CH_TS_X1 3
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#define PCAP_ADC_CH_TS_X2 4
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#define PCAP_ADC_CH_TS_Y1 5
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#define PCAP_ADC_CH_TS_Y2 6
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#define PCAP_ADC_T_NOW 0
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#define PCAP_ADC_T_IN_BURST 1
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#define PCAP_ADC_T_OUT_BURST 2
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#define PCAP_ADC_ATO_IN_BURST 6
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#define PCAP_ADC_ATO_OUT_BURST 0
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#define PCAP_ADC_TS_M_XY 1
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#define PCAP_ADC_TS_M_PRESSURE 2
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#define PCAP_ADC_TS_M_PLATE_X 3
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#define PCAP_ADC_TS_M_PLATE_Y 4
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#define PCAP_ADC_TS_M_STANDBY 5
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#define PCAP_ADC_TS_M_NONTS 6
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#define PCAP_ADR_ADD1_MASK 0x000003ff
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#define PCAP_ADR_ADD1_SHIFT 0
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#define PCAP_ADR_ADD2_MASK 0x000ffc00
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#define PCAP_ADR_ADD2_SHIFT 10
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#define PCAP_ADR_ADINC1 (1 << 20)
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#define PCAP_ADR_ADINC2 (1 << 21)
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#define PCAP_ADR_ASC (1 << 22)
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#define PCAP_ADR_ONESHOT (1 << 23)
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#define PCAP_BUSCTRL_FSENB (1 << 0)
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#define PCAP_BUSCTRL_USB_SUSPEND (1 << 1)
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#define PCAP_BUSCTRL_USB_PU (1 << 2)
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#define PCAP_BUSCTRL_USB_PD (1 << 3)
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#define PCAP_BUSCTRL_VUSB_EN (1 << 4)
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#define PCAP_BUSCTRL_USB_PS (1 << 5)
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#define PCAP_BUSCTRL_VUSB_MSTR_EN (1 << 6)
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#define PCAP_BUSCTRL_VBUS_PD_ENB (1 << 7)
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#define PCAP_BUSCTRL_CURRLIM (1 << 8)
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#define PCAP_BUSCTRL_RS232ENB (1 << 9)
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#define PCAP_BUSCTRL_RS232_DIR (1 << 10)
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#define PCAP_BUSCTRL_SE0_CONN (1 << 11)
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#define PCAP_BUSCTRL_USB_PDM (1 << 12)
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#define PCAP_BUSCTRL_BUS_PRI_ADJ (1 << 24)
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/* leds */
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#define PCAP_LED0 0
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#define PCAP_LED1 1
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#define PCAP_BL0 2
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#define PCAP_BL1 3
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#define PCAP_LED_3MA 0
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#define PCAP_LED_4MA 1
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#define PCAP_LED_5MA 2
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#define PCAP_LED_9MA 3
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#define PCAP_LED_T_MASK 0xf
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#define PCAP_LED_C_MASK 0x3
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#define PCAP_BL_MASK 0x1f
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#define PCAP_BL0_SHIFT 0
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#define PCAP_LED0_EN (1 << 5)
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#define PCAP_LED1_EN (1 << 6)
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#define PCAP_LED0_T_SHIFT 7
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#define PCAP_LED1_T_SHIFT 11
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#define PCAP_LED0_C_SHIFT 15
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#define PCAP_LED1_C_SHIFT 17
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#define PCAP_BL1_SHIFT 20
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/* RTC */
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#define PCAP_RTC_DAY_MASK 0x3fff
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#define PCAP_RTC_TOD_MASK 0xffff
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#define PCAP_RTC_PC_MASK 0x7
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#define SEC_PER_DAY 86400
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#endif
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