/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2014 Free Electrons
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* Copyright (C) 2014 Atmel
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*
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* Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
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*/
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#ifndef __LINUX_MFD_HLCDC_H
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#define __LINUX_MFD_HLCDC_H
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#include <linux/clk.h>
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#include <linux/regmap.h>
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#define ATMEL_HLCDC_CFG(i) ((i) * 0x4)
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#define ATMEL_HLCDC_SIG_CFG LCDCFG(5)
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#define ATMEL_HLCDC_HSPOL BIT(0)
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#define ATMEL_HLCDC_VSPOL BIT(1)
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#define ATMEL_HLCDC_VSPDLYS BIT(2)
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#define ATMEL_HLCDC_VSPDLYE BIT(3)
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#define ATMEL_HLCDC_DISPPOL BIT(4)
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#define ATMEL_HLCDC_DITHER BIT(6)
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#define ATMEL_HLCDC_DISPDLY BIT(7)
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#define ATMEL_HLCDC_MODE_MASK GENMASK(9, 8)
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#define ATMEL_HLCDC_PP BIT(10)
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#define ATMEL_HLCDC_VSPSU BIT(12)
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#define ATMEL_HLCDC_VSPHO BIT(13)
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#define ATMEL_HLCDC_GUARDTIME_MASK GENMASK(20, 16)
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#define ATMEL_HLCDC_EN 0x20
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#define ATMEL_HLCDC_DIS 0x24
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#define ATMEL_HLCDC_SR 0x28
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#define ATMEL_HLCDC_IER 0x2c
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#define ATMEL_HLCDC_IDR 0x30
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#define ATMEL_HLCDC_IMR 0x34
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#define ATMEL_HLCDC_ISR 0x38
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#define ATMEL_HLCDC_CLKPOL BIT(0)
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#define ATMEL_HLCDC_CLKSEL BIT(2)
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#define ATMEL_HLCDC_CLKPWMSEL BIT(3)
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#define ATMEL_HLCDC_CGDIS(i) BIT(8 + (i))
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#define ATMEL_HLCDC_CLKDIV_SHFT 16
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#define ATMEL_HLCDC_CLKDIV_MASK GENMASK(23, 16)
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#define ATMEL_HLCDC_CLKDIV(div) ((div - 2) << ATMEL_HLCDC_CLKDIV_SHFT)
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#define ATMEL_HLCDC_PIXEL_CLK BIT(0)
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#define ATMEL_HLCDC_SYNC BIT(1)
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#define ATMEL_HLCDC_DISP BIT(2)
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#define ATMEL_HLCDC_PWM BIT(3)
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#define ATMEL_HLCDC_SIP BIT(4)
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#define ATMEL_HLCDC_SOF BIT(0)
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#define ATMEL_HLCDC_SYNCDIS BIT(1)
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#define ATMEL_HLCDC_FIFOERR BIT(4)
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#define ATMEL_HLCDC_LAYER_STATUS(x) BIT((x) + 8)
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/**
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* Structure shared by the MFD device and its subdevices.
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*
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* @regmap: register map used to access HLCDC IP registers
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* @periph_clk: the hlcdc peripheral clock
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* @sys_clk: the hlcdc system clock
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* @slow_clk: the system slow clk
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* @irq: the hlcdc irq
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*/
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struct atmel_hlcdc {
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struct regmap *regmap;
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struct clk *periph_clk;
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struct clk *sys_clk;
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struct clk *slow_clk;
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int irq;
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};
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#endif /* __LINUX_MFD_HLCDC_H */
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