/*
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* Copyright (C) 2016 Rockchip Electronics Co., Ltd.
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* Authors:
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* Zhiqin Wei <wzq@rock-chips.com>
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef _RGA_DRIVER_H_
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#define _RGA_DRIVER_H_
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#include <asm/ioctl.h>
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/* Use 'r' as magic number */
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#define RGA_IOC_MAGIC 'r'
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#define RGA_IOW(nr, type) _IOW(RGA_IOC_MAGIC, nr, type)
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#define RGA_IOR(nr, type) _IOR(RGA_IOC_MAGIC, nr, type)
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#define RGA_IOWR(nr, type) _IOWR(RGA_IOC_MAGIC, nr, type)
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#define RGA_IOC_GET_DRVIER_VERSION RGA_IOR(0x1, struct rga_version_t)
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#define RGA_IOC_GET_HW_VERSION RGA_IOR(0x2, struct rga_hw_versions_t)
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#define RGA_IOC_IMPORT_BUFFER RGA_IOWR(0x3, struct rga_buffer_pool)
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#define RGA_IOC_RELEASE_BUFFER RGA_IOW(0x4, struct rga_buffer_pool)
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#define RGA_START_CONFIG RGA_IOR(0x5, uint32_t)
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#define RGA_END_CONFIG RGA_IOWR(0x6, struct rga_user_ctx_t)
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#define RGA_CMD_CONFIG RGA_IOWR(0x7, struct rga_user_ctx_t)
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#define RGA_CANCEL_CONFIG RGA_IOWR(0x8, uint32_t)
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#define RGA_BLIT_SYNC 0x5017
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#define RGA_BLIT_ASYNC 0x5018
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#define RGA_FLUSH 0x5019
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#define RGA_GET_RESULT 0x501a
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#define RGA_GET_VERSION 0x501b
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#define RGA2_BLIT_SYNC 0x6017
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#define RGA2_BLIT_ASYNC 0x6018
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#define RGA2_FLUSH 0x6019
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#define RGA2_GET_RESULT 0x601a
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#define RGA2_GET_VERSION 0x601b
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#define RGA_REG_CTRL_LEN 0x8 /* 8 */
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#define RGA_REG_CMD_LEN 0x1c /* 28 */
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#define RGA_CMD_BUF_SIZE 0x700 /* 16*28*4 */
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#ifndef ENABLE
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#define ENABLE 1
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#endif
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#ifndef DISABLE
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#define DISABLE 0
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#endif
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enum rga_memory_type {
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RGA_DMA_BUFFER = 0,
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RGA_VIRTUAL_ADDRESS,
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RGA_PHYSICAL_ADDRESS
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};
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/* RGA process mode enum */
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enum {
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bitblt_mode = 0x0,
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color_palette_mode = 0x1,
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color_fill_mode = 0x2,
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line_point_drawing_mode = 0x3,
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blur_sharp_filter_mode = 0x4,
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pre_scaling_mode = 0x5,
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update_palette_table_mode = 0x6,
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update_patten_buff_mode = 0x7,
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};
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enum {
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rop_enable_mask = 0x2,
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dither_enable_mask = 0x8,
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fading_enable_mask = 0x10,
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PD_enbale_mask = 0x20,
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};
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enum {
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yuv2rgb_mode0 = 0x0, /* BT.601 MPEG */
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yuv2rgb_mode1 = 0x1, /* BT.601 JPEG */
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yuv2rgb_mode2 = 0x2, /* BT.709 */
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rgb2yuv_601_full = 0x1 << 8,
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rgb2yuv_709_full = 0x2 << 8,
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yuv2yuv_601_limit_2_709_limit = 0x3 << 8,
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yuv2yuv_601_limit_2_709_full = 0x4 << 8,
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yuv2yuv_709_limit_2_601_limit = 0x5 << 8,
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yuv2yuv_709_limit_2_601_full = 0x6 << 8, //not support
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yuv2yuv_601_full_2_709_limit = 0x7 << 8,
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yuv2yuv_601_full_2_709_full = 0x8 << 8, //not support
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yuv2yuv_709_full_2_601_limit = 0x9 << 8, //not support
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yuv2yuv_709_full_2_601_full = 0xa << 8, //not support
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full_csc_mask = 0xf00,
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};
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/* RGA rotate mode */
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enum {
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rotate_mode0 = 0x0, /* no rotate */
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rotate_mode1 = 0x1, /* rotate */
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rotate_mode2 = 0x2, /* x_mirror */
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rotate_mode3 = 0x3, /* y_mirror */
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};
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enum {
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color_palette_mode0 = 0x0, /* 1K */
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color_palette_mode1 = 0x1, /* 2K */
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color_palette_mode2 = 0x2, /* 4K */
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color_palette_mode3 = 0x3, /* 8K */
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};
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enum {
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BB_BYPASS = 0x0, /* no rotate */
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BB_ROTATE = 0x1, /* rotate */
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BB_X_MIRROR = 0x2, /* x_mirror */
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BB_Y_MIRROR = 0x3 /* y_mirror */
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};
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enum {
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nearby = 0x0, /* no rotate */
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bilinear = 0x1, /* rotate */
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bicubic = 0x2, /* x_mirror */
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};
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#define RGA_SCHED_PRIORITY_DEFAULT 0
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#define RGA_SCHED_PRIORITY_MAX 6
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enum {
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RGA3_SCHEDULER_CORE0 = 1 << 0,
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RGA3_SCHEDULER_CORE1 = 1 << 1,
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RGA2_SCHEDULER_CORE0 = 1 << 2,
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};
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/*
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// Alpha Red Green Blue
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{ 4, 32, {{32,24, 8, 0, 16, 8, 24,16 }}, GGL_RGBA }, // RK_FORMAT_RGBA_8888
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{ 4, 24, {{ 0, 0, 8, 0, 16, 8, 24,16 }}, GGL_RGB }, // RK_FORMAT_RGBX_8888
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{ 3, 24, {{ 0, 0, 8, 0, 16, 8, 24,16 }}, GGL_RGB }, // RK_FORMAT_RGB_888
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{ 4, 32, {{32,24, 24,16, 16, 8, 8, 0 }}, GGL_BGRA }, // RK_FORMAT_BGRA_8888
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{ 2, 16, {{ 0, 0, 16,11, 11, 5, 5, 0 }}, GGL_RGB }, // RK_FORMAT_RGB_565
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{ 2, 16, {{ 1, 0, 16,11, 11, 6, 6, 1 }}, GGL_RGBA }, // RK_FORMAT_RGBA_5551
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{ 2, 16, {{ 4, 0, 16,12, 12, 8, 8, 4 }}, GGL_RGBA }, // RK_FORMAT_RGBA_4444
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{ 3, 24, {{ 0, 0, 24,16, 16, 8, 8, 0 }}, GGL_BGR }, // RK_FORMAT_BGB_888
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*/
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/* In order to be compatible with RK_FORMAT_XX and HAL_PIXEL_FORMAT_XX,
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* RK_FORMAT_XX is shifted to the left by 8 bits to distinguish. */
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typedef enum _Rga_SURF_FORMAT {
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RK_FORMAT_RGBA_8888 = 0x0 << 8,
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RK_FORMAT_RGBX_8888 = 0x1 << 8,
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RK_FORMAT_RGB_888 = 0x2 << 8,
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RK_FORMAT_BGRA_8888 = 0x3 << 8,
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RK_FORMAT_RGB_565 = 0x4 << 8,
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RK_FORMAT_RGBA_5551 = 0x5 << 8,
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RK_FORMAT_RGBA_4444 = 0x6 << 8,
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RK_FORMAT_BGR_888 = 0x7 << 8,
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RK_FORMAT_YCbCr_422_SP = 0x8 << 8,
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RK_FORMAT_YCbCr_422_P = 0x9 << 8,
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RK_FORMAT_YCbCr_420_SP = 0xa << 8,
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RK_FORMAT_YCbCr_420_P = 0xb << 8,
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RK_FORMAT_YCrCb_422_SP = 0xc << 8,
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RK_FORMAT_YCrCb_422_P = 0xd << 8,
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RK_FORMAT_YCrCb_420_SP = 0xe << 8,
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RK_FORMAT_YCrCb_420_P = 0xf << 8,
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RK_FORMAT_BPP1 = 0x10 << 8,
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RK_FORMAT_BPP2 = 0x11 << 8,
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RK_FORMAT_BPP4 = 0x12 << 8,
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RK_FORMAT_BPP8 = 0x13 << 8,
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RK_FORMAT_Y4 = 0x14 << 8,
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RK_FORMAT_YCbCr_400 = 0x15 << 8,
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RK_FORMAT_BGRX_8888 = 0x16 << 8,
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RK_FORMAT_YVYU_422 = 0x18 << 8,
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RK_FORMAT_YVYU_420 = 0x19 << 8,
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RK_FORMAT_VYUY_422 = 0x1a << 8,
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RK_FORMAT_VYUY_420 = 0x1b << 8,
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RK_FORMAT_YUYV_422 = 0x1c << 8,
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RK_FORMAT_YUYV_420 = 0x1d << 8,
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RK_FORMAT_UYVY_422 = 0x1e << 8,
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RK_FORMAT_UYVY_420 = 0x1f << 8,
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RK_FORMAT_YCbCr_420_SP_10B = 0x20 << 8,
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RK_FORMAT_YCrCb_420_SP_10B = 0x21 << 8,
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RK_FORMAT_YCbCr_422_SP_10B = 0x22 << 8,
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RK_FORMAT_YCrCb_422_SP_10B = 0x23 << 8,
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/* For compatibility with misspellings */
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RK_FORMAT_YCbCr_422_10b_SP = RK_FORMAT_YCbCr_422_SP_10B,
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RK_FORMAT_YCrCb_422_10b_SP = RK_FORMAT_YCrCb_422_SP_10B,
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RK_FORMAT_BGR_565 = 0x24 << 8,
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RK_FORMAT_BGRA_5551 = 0x25 << 8,
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RK_FORMAT_BGRA_4444 = 0x26 << 8,
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RK_FORMAT_ARGB_8888 = 0x28 << 8,
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RK_FORMAT_XRGB_8888 = 0x29 << 8,
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RK_FORMAT_ARGB_5551 = 0x2a << 8,
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RK_FORMAT_ARGB_4444 = 0x2b << 8,
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RK_FORMAT_ABGR_8888 = 0x2c << 8,
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RK_FORMAT_XBGR_8888 = 0x2d << 8,
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RK_FORMAT_ABGR_5551 = 0x2e << 8,
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RK_FORMAT_ABGR_4444 = 0x2f << 8,
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RK_FORMAT_RGBA2BPP = 0x30 << 8,
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RK_FORMAT_UNKNOWN = 0x100 << 8,
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} RgaSURF_FORMAT;
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/* RGA3 rd_mode */
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enum
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{
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raster_mode = 0x1 << 0,
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fbc_mode = 0x1 << 1,
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tile_mode = 0x1 << 2,
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};
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typedef struct rga_img_info_t {
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uint64_t yrgb_addr; /* yrgb mem addr */
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uint64_t uv_addr; /* cb/cr mem addr */
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uint64_t v_addr; /* cr mem addr */
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uint32_t format; //definition by RK_FORMAT
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uint16_t act_w;
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uint16_t act_h;
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uint16_t x_offset;
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uint16_t y_offset;
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uint16_t vir_w;
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uint16_t vir_h;
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uint16_t endian_mode; //for BPP
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uint16_t alpha_swap;
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//used by RGA3
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uint16_t rotate_mode;
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uint16_t rd_mode;
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uint16_t is_10b_compact;
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uint16_t is_10b_endian;
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uint16_t enable;
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}
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rga_img_info_t;
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typedef struct POINT {
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uint16_t x;
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uint16_t y;
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}
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POINT;
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typedef struct RECT {
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uint16_t xmin;
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uint16_t xmax; // width - 1
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uint16_t ymin;
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uint16_t ymax; // height - 1
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} RECT;
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typedef struct MMU {
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uint8_t mmu_en;
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uint64_t base_addr;
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uint32_t mmu_flag; /* [0] mmu enable [1] src_flush [2] dst_flush [3] CMD_flush [4~5] page size*/
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} MMU;
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typedef struct COLOR_FILL {
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int16_t gr_x_a;
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int16_t gr_y_a;
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int16_t gr_x_b;
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int16_t gr_y_b;
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int16_t gr_x_g;
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int16_t gr_y_g;
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int16_t gr_x_r;
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int16_t gr_y_r;
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//u8 cp_gr_saturation;
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}
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COLOR_FILL;
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typedef struct FADING {
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uint8_t b;
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uint8_t g;
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uint8_t r;
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uint8_t res;
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}
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FADING;
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typedef struct line_draw_t {
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POINT start_point; /* LineDraw_start_point */
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POINT end_point; /* LineDraw_end_point */
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uint32_t color; /* LineDraw_color */
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uint32_t flag; /* (enum) LineDrawing mode sel */
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uint32_t line_width; /* range 1~16 */
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}
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line_draw_t;
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/* color space convert coefficient. */
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typedef struct csc_coe_t {
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int16_t r_v;
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int16_t g_y;
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int16_t b_u;
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int32_t off;
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} csc_coe_t;
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typedef struct full_csc_t {
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uint8_t flag;
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csc_coe_t coe_y;
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csc_coe_t coe_u;
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csc_coe_t coe_v;
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} full_csc_t;
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struct rga_mosaic_info {
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uint8_t enable;
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uint8_t mode;
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};
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struct rga_pre_intr_info {
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uint8_t enable;
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uint8_t read_intr_en;
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uint8_t write_intr_en;
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uint8_t read_hold_en;
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uint32_t read_threshold;
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uint32_t write_start;
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uint32_t write_step;
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};
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/* MAX(min, (max - channel_value)) */
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struct rga_osd_invert_factor {
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uint8_t alpha_max;
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uint8_t alpha_min;
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uint8_t yg_max;
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uint8_t yg_min;
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uint8_t crb_max;
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uint8_t crb_min;
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};
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struct rga_color {
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union {
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struct {
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uint8_t red;
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uint8_t green;
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uint8_t blue;
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uint8_t alpha;
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};
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uint32_t value;
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};
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};
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struct rga_osd_bpp2 {
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uint8_t ac_swap; // ac swap flag
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// 0: CA
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// 1: AC
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uint8_t endian_swap; // rgba2bpp endian swap
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// 0: Big endian
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// 1: Little endian
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struct rga_color color0;
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struct rga_color color1;
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};
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struct rga_osd_mode_ctrl {
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uint8_t mode; // OSD cal mode:
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// 0b'1: statistics mode
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// 1b'1: auto inversion overlap mode
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uint8_t direction_mode; // horizontal or vertical
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// 0: horizontal
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// 1: vertical
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uint8_t width_mode; // using @fix_width or LUT width
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// 0: fix width
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// 1: LUT width
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uint16_t block_fix_width; // OSD block fixed width
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// real width = (fix_width + 1) * 2
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uint8_t block_num; // OSD block num
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uint16_t flags_index; // auto invert flags index
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/* invertion config */
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uint8_t color_mode; // selete color
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// 0: src1 color
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// 1: config data color
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uint8_t invert_flags_mode; // invert flag selete
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// 0: use RAM flag
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// 1: usr last result
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uint8_t default_color_sel; // default color mode
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// 0: default is bright
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// 1: default is dark
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uint8_t invert_enable; // invert channel enable
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// 1 << 0: aplha enable
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// 1 << 1: Y/G disable
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// 1 << 2: C/RB disable
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uint8_t invert_mode; // invert cal mode
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// 0: normal(max-data)
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// 1: swap
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uint8_t invert_thresh; // if luma > thresh, osd_flag to be 1
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uint8_t unfix_index; // OSD width config index
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};
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struct rga_osd_info {
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uint8_t enable;
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struct rga_osd_mode_ctrl mode_ctrl;
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struct rga_osd_invert_factor cal_factor;
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struct rga_osd_bpp2 bpp2_info;
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union {
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struct {
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uint32_t last_flags1;
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uint32_t last_flags0;
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};
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uint64_t last_flags;
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};
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union {
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struct {
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uint32_t cur_flags1;
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uint32_t cur_flags0;
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};
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uint64_t cur_flags;
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};
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};
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#define RGA_VERSION_SIZE 16
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#define RGA_HW_SIZE 5
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struct rga_version_t {
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uint32_t major;
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uint32_t minor;
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uint32_t revision;
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uint8_t str[RGA_VERSION_SIZE];
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};
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struct rga_hw_versions_t {
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struct rga_version_t version[RGA_HW_SIZE];
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uint32_t size;
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};
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struct rga_memory_parm {
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uint32_t width;
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uint32_t height;
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uint32_t format;
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uint32_t size;
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};
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struct rga_external_buffer {
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uint64_t memory;
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uint32_t type;
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uint32_t handle;
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struct rga_memory_parm memory_info;
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uint8_t reserve[252];
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};
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struct rga_buffer_pool {
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uint64_t buffers;
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uint32_t size;
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};
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struct rga_req {
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uint8_t render_mode; /* (enum) process mode sel */
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rga_img_info_t src; /* src image info */
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rga_img_info_t dst; /* dst image info */
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rga_img_info_t pat; /* patten image info */
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uint64_t rop_mask_addr; /* rop4 mask addr */
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uint64_t LUT_addr; /* LUT addr */
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RECT clip; /* dst clip window default value is dst_vir */
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/* value from [0, w-1] / [0, h-1]*/
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int32_t sina; /* dst angle default value 0 16.16 scan from table */
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int32_t cosa; /* dst angle default value 0 16.16 scan from table */
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uint16_t alpha_rop_flag; /* alpha rop process flag */
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/* ([0] = 1 alpha_rop_enable) */
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/* ([1] = 1 rop enable) */
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/* ([2] = 1 fading_enable) */
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/* ([3] = 1 PD_enable) */
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/* ([4] = 1 alpha cal_mode_sel) */
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/* ([5] = 1 dither_enable) */
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/* ([6] = 1 gradient fill mode sel) */
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/* ([7] = 1 AA_enable) */
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/* ([8] = 1 nn_quantize) */
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/* ([9] = 1 Real color mode) */
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uint8_t scale_mode; /* 0 nearst / 1 bilnear / 2 bicubic */
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uint32_t color_key_max; /* color key max */
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uint32_t color_key_min; /* color key min */
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uint32_t fg_color; /* foreground color */
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uint32_t bg_color; /* background color */
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COLOR_FILL gr_color; /* color fill use gradient */
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line_draw_t line_draw_info;
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FADING fading;
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uint8_t PD_mode; /* porter duff alpha mode sel */
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uint8_t alpha_global_value; /* global alpha value */
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uint16_t rop_code; /* rop2/3/4 code scan from rop code table*/
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uint8_t bsfilter_flag; /* [2] 0 blur 1 sharp / [1:0] filter_type*/
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uint8_t palette_mode; /* (enum) color palatte 0/1bpp, 1/2bpp 2/4bpp 3/8bpp*/
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uint8_t yuv2rgb_mode; /* (enum) BT.601 MPEG / BT.601 JPEG / BT.709 */
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uint8_t endian_mode; /* 0/big endian 1/little endian*/
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uint8_t rotate_mode; /* (enum) rotate mode */
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/* 0x0, no rotate */
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/* 0x1, rotate */
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/* 0x2, x_mirror */
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/* 0x3, y_mirror */
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uint8_t color_fill_mode; /* 0 solid color / 1 patten color */
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MMU mmu_info; /* mmu information */
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uint8_t alpha_rop_mode; /* ([0~1] alpha mode) */
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/* ([2~3] rop mode) */
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/* ([4] zero mode en) */
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/* ([5] dst alpha mode) (RGA1) */
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uint8_t src_trans_mode;
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uint8_t dither_mode;
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full_csc_t full_csc; /* full color space convert */
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int32_t in_fence_fd;
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uint8_t core;
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uint8_t priority;
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int32_t out_fence_fd;
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uint8_t handle_flag;
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/* RGA2 1106 add */
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struct rga_mosaic_info mosaic_info;
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uint8_t uvhds_mode;
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uint8_t uvvds_mode;
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struct rga_osd_info osd_info;
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struct rga_pre_intr_info pre_intr_info;
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uint8_t reservr[59];
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};
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struct rga_user_ctx_t {
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uint64_t cmd_ptr;
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uint32_t cmd_num;
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uint32_t id;
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uint32_t sync_mode;
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uint32_t out_fence_fd;
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uint32_t mpi_config_flags;
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uint8_t reservr[124];
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};
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#ifdef __cplusplus
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}
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#endif
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#endif /*_RK29_IPP_DRIVER_H_*/
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