Prior Operation     Subsequent Operation 
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                                  ---------------  --------------------------- 
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                               C  Self  R  W  RMW  Self  R  W  DR  DW  RMW  SV 
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                              --  ----  -  -  ---  ----  -  -  --  --  ---  -- 
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Relaxed store                        Y                                       Y 
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Relaxed load                         Y                          Y   Y        Y 
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Relaxed RMW operation                Y                          Y   Y        Y 
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rcu_dereference()                    Y                          Y   Y        Y 
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Successful *_acquire()               R                   Y  Y   Y   Y    Y   Y 
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Successful *_release()         C        Y  Y    Y     W                      Y 
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smp_rmb()                               Y       R        Y      Y        R 
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smp_wmb()                                  Y    W           Y       Y    W 
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smp_mb() & synchronize_rcu()  CP        Y  Y    Y        Y  Y   Y   Y    Y 
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Successful full non-void RMW  CP     Y  Y  Y    Y     Y  Y  Y   Y   Y    Y   Y 
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smp_mb__before_atomic()       CP        Y  Y    Y        a  a   a   a    Y 
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smp_mb__after_atomic()        CP        a  a    Y        Y  Y   Y   Y    Y 
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Key:    Relaxed:  A relaxed operation is either READ_ONCE(), WRITE_ONCE(), 
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          a *_relaxed() RMW operation, an unsuccessful RMW 
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          operation, a non-value-returning RMW operation such 
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          as atomic_inc(), or one of the atomic*_read() and 
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          atomic*_set() family of operations. 
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    C:      Ordering is cumulative 
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    P:      Ordering propagates 
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    R:      Read, for example, READ_ONCE(), or read portion of RMW 
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    W:      Write, for example, WRITE_ONCE(), or write portion of RMW 
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    Y:      Provides ordering 
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    a:      Provides ordering given intervening RMW atomic operation 
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    DR:      Dependent read (address dependency) 
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    DW:      Dependent write (address, data, or control dependency) 
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    RMW:      Atomic read-modify-write operation 
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    SELF:      Orders self, as opposed to accesses before and/or after 
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    SV:      Orders later accesses to the same variable 
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