/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
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/* Copyright(c) 2015-17 Intel Corporation. */
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#ifndef __SDW_REGISTERS_H
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#define __SDW_REGISTERS_H
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/*
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* SDW registers as defined by MIPI 1.2 Spec
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*/
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#define SDW_REGADDR GENMASK(14, 0)
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#define SDW_SCP_ADDRPAGE2_MASK GENMASK(22, 15)
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#define SDW_SCP_ADDRPAGE1_MASK GENMASK(30, 23)
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#define SDW_REG_NO_PAGE 0x00008000
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#define SDW_REG_OPTIONAL_PAGE 0x00010000
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#define SDW_REG_MAX 0x80000000
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#define SDW_DPN_SIZE 0x100
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#define SDW_BANK1_OFFSET 0x10
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/*
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* DP0 Interrupt register & bits
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*
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* Spec treats Status (RO) and Clear (WC) as separate but they are same
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* address, so treat as same register with WC.
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*/
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/* both INT and STATUS register are same */
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#define SDW_DP0_INT 0x0
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#define SDW_DP0_INTMASK 0x1
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#define SDW_DP0_PORTCTRL 0x2
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#define SDW_DP0_BLOCKCTRL1 0x3
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#define SDW_DP0_PREPARESTATUS 0x4
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#define SDW_DP0_PREPARECTRL 0x5
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#define SDW_DP0_INT_TEST_FAIL BIT(0)
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#define SDW_DP0_INT_PORT_READY BIT(1)
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#define SDW_DP0_INT_BRA_FAILURE BIT(2)
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#define SDW_DP0_SDCA_CASCADE BIT(3)
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/* BIT(4) not allocated in SoundWire specification 1.2 */
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#define SDW_DP0_INT_IMPDEF1 BIT(5)
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#define SDW_DP0_INT_IMPDEF2 BIT(6)
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#define SDW_DP0_INT_IMPDEF3 BIT(7)
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#define SDW_DP0_PORTCTRL_DATAMODE GENMASK(3, 2)
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#define SDW_DP0_PORTCTRL_NXTINVBANK BIT(4)
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#define SDW_DP0_PORTCTRL_BPT_PAYLD GENMASK(7, 6)
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#define SDW_DP0_CHANNELEN 0x20
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#define SDW_DP0_SAMPLECTRL1 0x22
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#define SDW_DP0_SAMPLECTRL2 0x23
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#define SDW_DP0_OFFSETCTRL1 0x24
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#define SDW_DP0_OFFSETCTRL2 0x25
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#define SDW_DP0_HCTRL 0x26
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#define SDW_DP0_LANECTRL 0x28
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/* Both INT and STATUS register are same */
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#define SDW_SCP_INT1 0x40
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#define SDW_SCP_INTMASK1 0x41
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#define SDW_SCP_INT1_PARITY BIT(0)
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#define SDW_SCP_INT1_BUS_CLASH BIT(1)
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#define SDW_SCP_INT1_IMPL_DEF BIT(2)
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#define SDW_SCP_INT1_SCP2_CASCADE BIT(7)
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#define SDW_SCP_INT1_PORT0_3 GENMASK(6, 3)
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#define SDW_SCP_INTSTAT2 0x42
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#define SDW_SCP_INTSTAT2_SCP3_CASCADE BIT(7)
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#define SDW_SCP_INTSTAT2_PORT4_10 GENMASK(6, 0)
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#define SDW_SCP_INTSTAT3 0x43
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#define SDW_SCP_INTSTAT3_PORT11_14 GENMASK(3, 0)
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/* Number of interrupt status registers */
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#define SDW_NUM_INT_STAT_REGISTERS 3
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/* Number of interrupt clear registers */
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#define SDW_NUM_INT_CLEAR_REGISTERS 1
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#define SDW_SCP_CTRL 0x44
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#define SDW_SCP_CTRL_CLK_STP_NOW BIT(1)
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#define SDW_SCP_CTRL_FORCE_RESET BIT(7)
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#define SDW_SCP_STAT 0x44
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#define SDW_SCP_STAT_CLK_STP_NF BIT(0)
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#define SDW_SCP_STAT_HPHY_NOK BIT(5)
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#define SDW_SCP_STAT_CURR_BANK BIT(6)
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#define SDW_SCP_SYSTEMCTRL 0x45
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#define SDW_SCP_SYSTEMCTRL_CLK_STP_PREP BIT(0)
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#define SDW_SCP_SYSTEMCTRL_CLK_STP_MODE BIT(2)
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#define SDW_SCP_SYSTEMCTRL_WAKE_UP_EN BIT(3)
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#define SDW_SCP_SYSTEMCTRL_HIGH_PHY BIT(4)
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#define SDW_SCP_SYSTEMCTRL_CLK_STP_MODE0 0
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#define SDW_SCP_SYSTEMCTRL_CLK_STP_MODE1 BIT(2)
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#define SDW_SCP_DEVNUMBER 0x46
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#define SDW_SCP_HIGH_PHY_CHECK 0x47
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#define SDW_SCP_ADDRPAGE1 0x48
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#define SDW_SCP_ADDRPAGE2 0x49
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#define SDW_SCP_KEEPEREN 0x4A
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#define SDW_SCP_BANKDELAY 0x4B
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#define SDW_SCP_COMMIT 0x4C
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#define SDW_SCP_BUS_CLOCK_BASE 0x4D
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#define SDW_SCP_BASE_CLOCK_FREQ GENMASK(2, 0)
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#define SDW_SCP_BASE_CLOCK_UNKNOWN 0x0
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#define SDW_SCP_BASE_CLOCK_19200000_HZ 0x1
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#define SDW_SCP_BASE_CLOCK_24000000_HZ 0x2
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#define SDW_SCP_BASE_CLOCK_24576000_HZ 0x3
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#define SDW_SCP_BASE_CLOCK_22579200_HZ 0x4
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#define SDW_SCP_BASE_CLOCK_32000000_HZ 0x5
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#define SDW_SCP_BASE_CLOCK_RESERVED 0x6
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#define SDW_SCP_BASE_CLOCK_IMP_DEF 0x7
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/* 0x4E is not allocated in SoundWire specification 1.2 */
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#define SDW_SCP_TESTMODE 0x4F
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#define SDW_SCP_DEVID_0 0x50
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#define SDW_SCP_DEVID_1 0x51
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#define SDW_SCP_DEVID_2 0x52
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#define SDW_SCP_DEVID_3 0x53
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#define SDW_SCP_DEVID_4 0x54
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#define SDW_SCP_DEVID_5 0x55
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/* Both INT and STATUS register are same */
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#define SDW_SCP_SDCA_INT1 0x58
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#define SDW_SCP_SDCA_INT_SDCA_0 BIT(0)
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#define SDW_SCP_SDCA_INT_SDCA_1 BIT(1)
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#define SDW_SCP_SDCA_INT_SDCA_2 BIT(2)
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#define SDW_SCP_SDCA_INT_SDCA_3 BIT(3)
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#define SDW_SCP_SDCA_INT_SDCA_4 BIT(4)
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#define SDW_SCP_SDCA_INT_SDCA_5 BIT(5)
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#define SDW_SCP_SDCA_INT_SDCA_6 BIT(6)
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#define SDW_SCP_SDCA_INT_SDCA_7 BIT(7)
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#define SDW_SCP_SDCA_INT2 0x59
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#define SDW_SCP_SDCA_INT_SDCA_8 BIT(0)
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#define SDW_SCP_SDCA_INT_SDCA_9 BIT(1)
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#define SDW_SCP_SDCA_INT_SDCA_10 BIT(2)
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#define SDW_SCP_SDCA_INT_SDCA_11 BIT(3)
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#define SDW_SCP_SDCA_INT_SDCA_12 BIT(4)
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#define SDW_SCP_SDCA_INT_SDCA_13 BIT(5)
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#define SDW_SCP_SDCA_INT_SDCA_14 BIT(6)
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#define SDW_SCP_SDCA_INT_SDCA_15 BIT(7)
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#define SDW_SCP_SDCA_INT3 0x5A
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#define SDW_SCP_SDCA_INT_SDCA_16 BIT(0)
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#define SDW_SCP_SDCA_INT_SDCA_17 BIT(1)
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#define SDW_SCP_SDCA_INT_SDCA_18 BIT(2)
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#define SDW_SCP_SDCA_INT_SDCA_19 BIT(3)
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#define SDW_SCP_SDCA_INT_SDCA_20 BIT(4)
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#define SDW_SCP_SDCA_INT_SDCA_21 BIT(5)
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#define SDW_SCP_SDCA_INT_SDCA_22 BIT(6)
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#define SDW_SCP_SDCA_INT_SDCA_23 BIT(7)
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#define SDW_SCP_SDCA_INT4 0x5B
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#define SDW_SCP_SDCA_INT_SDCA_24 BIT(0)
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#define SDW_SCP_SDCA_INT_SDCA_25 BIT(1)
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#define SDW_SCP_SDCA_INT_SDCA_26 BIT(2)
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#define SDW_SCP_SDCA_INT_SDCA_27 BIT(3)
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#define SDW_SCP_SDCA_INT_SDCA_28 BIT(4)
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#define SDW_SCP_SDCA_INT_SDCA_29 BIT(5)
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#define SDW_SCP_SDCA_INT_SDCA_30 BIT(6)
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/* BIT(7) not allocated in SoundWire 1.2 specification */
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#define SDW_SCP_SDCA_INTMASK1 0x5C
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#define SDW_SCP_SDCA_INTMASK_SDCA_0 BIT(0)
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#define SDW_SCP_SDCA_INTMASK_SDCA_1 BIT(1)
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#define SDW_SCP_SDCA_INTMASK_SDCA_2 BIT(2)
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#define SDW_SCP_SDCA_INTMASK_SDCA_3 BIT(3)
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#define SDW_SCP_SDCA_INTMASK_SDCA_4 BIT(4)
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#define SDW_SCP_SDCA_INTMASK_SDCA_5 BIT(5)
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#define SDW_SCP_SDCA_INTMASK_SDCA_6 BIT(6)
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#define SDW_SCP_SDCA_INTMASK_SDCA_7 BIT(7)
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#define SDW_SCP_SDCA_INTMASK2 0x5D
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#define SDW_SCP_SDCA_INTMASK_SDCA_8 BIT(0)
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#define SDW_SCP_SDCA_INTMASK_SDCA_9 BIT(1)
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#define SDW_SCP_SDCA_INTMASK_SDCA_10 BIT(2)
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#define SDW_SCP_SDCA_INTMASK_SDCA_11 BIT(3)
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#define SDW_SCP_SDCA_INTMASK_SDCA_12 BIT(4)
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#define SDW_SCP_SDCA_INTMASK_SDCA_13 BIT(5)
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#define SDW_SCP_SDCA_INTMASK_SDCA_14 BIT(6)
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#define SDW_SCP_SDCA_INTMASK_SDCA_15 BIT(7)
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#define SDW_SCP_SDCA_INTMASK3 0x5E
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#define SDW_SCP_SDCA_INTMASK_SDCA_16 BIT(0)
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#define SDW_SCP_SDCA_INTMASK_SDCA_17 BIT(1)
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#define SDW_SCP_SDCA_INTMASK_SDCA_18 BIT(2)
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#define SDW_SCP_SDCA_INTMASK_SDCA_19 BIT(3)
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#define SDW_SCP_SDCA_INTMASK_SDCA_20 BIT(4)
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#define SDW_SCP_SDCA_INTMASK_SDCA_21 BIT(5)
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#define SDW_SCP_SDCA_INTMASK_SDCA_22 BIT(6)
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#define SDW_SCP_SDCA_INTMASK_SDCA_23 BIT(7)
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#define SDW_SCP_SDCA_INTMASK4 0x5F
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#define SDW_SCP_SDCA_INTMASK_SDCA_24 BIT(0)
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#define SDW_SCP_SDCA_INTMASK_SDCA_25 BIT(1)
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#define SDW_SCP_SDCA_INTMASK_SDCA_26 BIT(2)
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#define SDW_SCP_SDCA_INTMASK_SDCA_27 BIT(3)
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#define SDW_SCP_SDCA_INTMASK_SDCA_28 BIT(4)
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#define SDW_SCP_SDCA_INTMASK_SDCA_29 BIT(5)
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#define SDW_SCP_SDCA_INTMASK_SDCA_30 BIT(6)
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/* BIT(7) not allocated in SoundWire 1.2 specification */
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/* Banked Registers */
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#define SDW_SCP_FRAMECTRL_B0 0x60
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#define SDW_SCP_FRAMECTRL_B1 (0x60 + SDW_BANK1_OFFSET)
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#define SDW_SCP_NEXTFRAME_B0 0x61
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#define SDW_SCP_NEXTFRAME_B1 (0x61 + SDW_BANK1_OFFSET)
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#define SDW_SCP_BUSCLOCK_SCALE_B0 0x62
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#define SDW_SCP_BUSCLOCK_SCALE_B1 (0x62 + SDW_BANK1_OFFSET)
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#define SDW_SCP_CLOCK_SCALE GENMASK(3, 0)
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/* PHY registers - CTRL and STAT are the same address */
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#define SDW_SCP_PHY_OUT_CTRL_0 0x80
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#define SDW_SCP_PHY_OUT_CTRL_1 0x81
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#define SDW_SCP_PHY_OUT_CTRL_2 0x82
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#define SDW_SCP_PHY_OUT_CTRL_3 0x83
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#define SDW_SCP_PHY_OUT_CTRL_4 0x84
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#define SDW_SCP_PHY_OUT_CTRL_5 0x85
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#define SDW_SCP_PHY_OUT_CTRL_6 0x86
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#define SDW_SCP_PHY_OUT_CTRL_7 0x87
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#define SDW_SCP_CAP_LOAD_CTRL GENMASK(2, 0)
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#define SDW_SCP_DRIVE_STRENGTH_CTRL GENMASK(5, 3)
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#define SDW_SCP_SLEW_TIME_CTRL GENMASK(7, 6)
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/* Both INT and STATUS register is same */
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#define SDW_DPN_INT(n) (0x0 + SDW_DPN_SIZE * (n))
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#define SDW_DPN_INTMASK(n) (0x1 + SDW_DPN_SIZE * (n))
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#define SDW_DPN_PORTCTRL(n) (0x2 + SDW_DPN_SIZE * (n))
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#define SDW_DPN_BLOCKCTRL1(n) (0x3 + SDW_DPN_SIZE * (n))
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#define SDW_DPN_PREPARESTATUS(n) (0x4 + SDW_DPN_SIZE * (n))
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#define SDW_DPN_PREPARECTRL(n) (0x5 + SDW_DPN_SIZE * (n))
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#define SDW_DPN_INT_TEST_FAIL BIT(0)
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#define SDW_DPN_INT_PORT_READY BIT(1)
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#define SDW_DPN_INT_IMPDEF1 BIT(5)
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#define SDW_DPN_INT_IMPDEF2 BIT(6)
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#define SDW_DPN_INT_IMPDEF3 BIT(7)
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#define SDW_DPN_PORTCTRL_FLOWMODE GENMASK(1, 0)
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#define SDW_DPN_PORTCTRL_DATAMODE GENMASK(3, 2)
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#define SDW_DPN_PORTCTRL_NXTINVBANK BIT(4)
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#define SDW_DPN_BLOCKCTRL1_WDLEN GENMASK(5, 0)
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#define SDW_DPN_PREPARECTRL_CH_PREP GENMASK(7, 0)
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#define SDW_DPN_CHANNELEN_B0(n) (0x20 + SDW_DPN_SIZE * (n))
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#define SDW_DPN_CHANNELEN_B1(n) (0x30 + SDW_DPN_SIZE * (n))
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#define SDW_DPN_BLOCKCTRL2_B0(n) (0x21 + SDW_DPN_SIZE * (n))
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#define SDW_DPN_BLOCKCTRL2_B1(n) (0x31 + SDW_DPN_SIZE * (n))
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#define SDW_DPN_SAMPLECTRL1_B0(n) (0x22 + SDW_DPN_SIZE * (n))
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#define SDW_DPN_SAMPLECTRL1_B1(n) (0x32 + SDW_DPN_SIZE * (n))
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#define SDW_DPN_SAMPLECTRL2_B0(n) (0x23 + SDW_DPN_SIZE * (n))
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#define SDW_DPN_SAMPLECTRL2_B1(n) (0x33 + SDW_DPN_SIZE * (n))
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#define SDW_DPN_OFFSETCTRL1_B0(n) (0x24 + SDW_DPN_SIZE * (n))
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#define SDW_DPN_OFFSETCTRL1_B1(n) (0x34 + SDW_DPN_SIZE * (n))
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#define SDW_DPN_OFFSETCTRL2_B0(n) (0x25 + SDW_DPN_SIZE * (n))
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#define SDW_DPN_OFFSETCTRL2_B1(n) (0x35 + SDW_DPN_SIZE * (n))
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#define SDW_DPN_HCTRL_B0(n) (0x26 + SDW_DPN_SIZE * (n))
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#define SDW_DPN_HCTRL_B1(n) (0x36 + SDW_DPN_SIZE * (n))
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#define SDW_DPN_BLOCKCTRL3_B0(n) (0x27 + SDW_DPN_SIZE * (n))
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#define SDW_DPN_BLOCKCTRL3_B1(n) (0x37 + SDW_DPN_SIZE * (n))
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#define SDW_DPN_LANECTRL_B0(n) (0x28 + SDW_DPN_SIZE * (n))
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#define SDW_DPN_LANECTRL_B1(n) (0x38 + SDW_DPN_SIZE * (n))
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#define SDW_DPN_SAMPLECTRL_LOW GENMASK(7, 0)
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#define SDW_DPN_SAMPLECTRL_HIGH GENMASK(15, 8)
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#define SDW_DPN_HCTRL_HSTART GENMASK(7, 4)
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#define SDW_DPN_HCTRL_HSTOP GENMASK(3, 0)
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#define SDW_NUM_CASC_PORT_INTSTAT1 4
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#define SDW_CASC_PORT_START_INTSTAT1 0
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#define SDW_CASC_PORT_MASK_INTSTAT1 0x8
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#define SDW_CASC_PORT_REG_OFFSET_INTSTAT1 0x0
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#define SDW_NUM_CASC_PORT_INTSTAT2 7
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#define SDW_CASC_PORT_START_INTSTAT2 4
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#define SDW_CASC_PORT_MASK_INTSTAT2 1
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#define SDW_CASC_PORT_REG_OFFSET_INTSTAT2 1
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#define SDW_NUM_CASC_PORT_INTSTAT3 4
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#define SDW_CASC_PORT_START_INTSTAT3 11
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#define SDW_CASC_PORT_MASK_INTSTAT3 1
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#define SDW_CASC_PORT_REG_OFFSET_INTSTAT3 2
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#endif /* __SDW_REGISTERS_H */
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