/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
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*/
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#ifndef __LINUX_REGULATOR_RK806_H
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#define __LINUX_REGULATOR_RK806_H
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#include <linux/regmap.h>
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#include <linux/regulator/driver.h>
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#include <linux/regulator/machine.h>
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#define RK806_POWER_EN0 0x0
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#define RK806_POWER_EN1 0x1
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#define RK806_POWER_EN2 0x2
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#define RK806_POWER_EN3 0x3
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#define RK806_POWER_EN4 0x4
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#define RK806_POWER_EN5 0x5
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#define RK806_POWER_SLP_EN0 0x6
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#define RK806_POWER_SLP_EN1 0x7
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#define RK806_POWER_SLP_EN2 0x8
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#define RK806_POWER_DISCHRG_EN0 0x9
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#define RK806_POWER_DISCHRG_EN1 0xA
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#define RK806_POWER_DISCHRG_EN2 0xB
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#define RK806_BUCK_FB_CONFIG 0xC
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#define RK806_SLP_LP_CONFIG 0xD
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#define RK806_POWER_FPWM_EN0 0xE
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#define RK806_POWER_FPWM_EN1 0xF
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#define RK806_BUCK1_CONFIG 0x10
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#define RK806_BUCK2_CONFIG 0x11
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#define RK806_BUCK3_CONFIG 0x12
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#define RK806_BUCK4_CONFIG 0x13
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#define RK806_BUCK5_CONFIG 0x14
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#define RK806_BUCK6_CONFIG 0x15
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#define RK806_BUCK7_CONFIG 0x16
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#define RK806_BUCK8_CONFIG 0x17
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#define RK806_BUCK9_CONFIG 0x18
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#define RK806_BUCK10_CONFIG 0x19
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#define RK806_BUCK1_ON_VSEL 0x1A
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#define RK806_BUCK2_ON_VSEL 0x1B
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#define RK806_BUCK3_ON_VSEL 0x1C
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#define RK806_BUCK4_ON_VSEL 0x1D
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#define RK806_BUCK5_ON_VSEL 0x1E
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#define RK806_BUCK6_ON_VSEL 0x1F
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#define RK806_BUCK7_ON_VSEL 0x20
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#define RK806_BUCK8_ON_VSEL 0x21
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#define RK806_BUCK9_ON_VSEL 0x22
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#define RK806_BUCK10_ON_VSEL 0x23
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#define RK806_BUCK1_SLP_VSEL 0x24
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#define RK806_BUCK2_SLP_VSEL 0x25
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#define RK806_BUCK3_SLP_VSEL 0x26
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#define RK806_BUCK4_SLP_VSEL 0x27
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#define RK806_BUCK5_SLP_VSEL 0x28
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#define RK806_BUCK6_SLP_VSEL 0x29
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#define RK806_BUCK7_SLP_VSEL 0x2A
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#define RK806_BUCK8_SLP_VSEL 0x2B
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#define RK806_BUCK9_SLP_VSEL 0x2D
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#define RK806_BUCK10_SLP_VSEL 0x2E
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#define RK806_BUCK_DEBUG1 0x30
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#define RK806_BUCK_DEBUG2 0x31
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#define RK806_BUCK_DEBUG3 0x32
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#define RK806_BUCK_DEBUG4 0x33
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#define RK806_BUCK_DEBUG5 0x34
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#define RK806_BUCK_DEBUG6 0x35
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#define RK806_BUCK_DEBUG7 0x36
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#define RK806_BUCK_DEBUG8 0x37
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#define RK806_BUCK_DEBUG9 0x38
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#define RK806_BUCK_DEBUG10 0x39
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#define RK806_BUCK_DEBUG11 0x3A
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#define RK806_BUCK_DEBUG12 0x3B
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#define RK806_BUCK_DEBUG13 0x3C
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#define RK806_BUCK_DEBUG14 0x3D
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#define RK806_BUCK_DEBUG15 0x3E
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#define RK806_BUCK_DEBUG16 0x3F
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#define RK806_BUCK_DEBUG17 0x40
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#define RK806_BUCK_DEBUG18 0x41
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#define RK806_NLDO_IMAX 0x42
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#define RK806_NLDO1_ON_VSEL 0x43
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#define RK806_NLDO2_ON_VSEL 0x44
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#define RK806_NLDO3_ON_VSEL 0x45
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#define RK806_NLDO4_ON_VSEL 0x46
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#define RK806_NLDO5_ON_VSEL 0x47
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#define RK806_NLDO1_SLP_VSEL 0x48
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#define RK806_NLDO2_SLP_VSEL 0x49
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#define RK806_NLDO3_SLP_VSEL 0x4A
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#define RK806_NLDO4_SLP_VSEL 0x4B
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#define RK806_NLDO5_SLP_VSEL 0x4C
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#define RK806_PLDO_IMAX 0x4D
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#define RK806_PLDO1_ON_VSEL 0x4E
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#define RK806_PLDO2_ON_VSEL 0x4F
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#define RK806_PLDO3_ON_VSEL 0x50
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#define RK806_PLDO4_ON_VSEL 0x51
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#define RK806_PLDO5_ON_VSEL 0x52
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#define RK806_PLDO6_ON_VSEL 0x53
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#define RK806_PLDO1_SLP_VSEL 0x54
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#define RK806_PLDO2_SLP_VSEL 0x55
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#define RK806_PLDO3_SLP_VSEL 0x56
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#define RK806_PLDO4_SLP_VSEL 0x57
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#define RK806_PLDO5_SLP_VSEL 0x58
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#define RK806_PLDO6_SLP_VSEL 0x59
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#define RK806_CHIP_NAME 0x5A
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#define RK806_CHIP_VER 0x5B
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#define RK806_OTP_VER 0x5C
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#define RK806_SYS_STS 0x5D
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#define RK806_SYS_CFG0 0x5E
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#define RK806_SYS_CFG1 0x5F
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#define RK806_SYS_OPTION 0x61
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#define RK806_SLEEP_CONFIG0 0x62
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#define RK806_SLEEP_CONFIG1 0x63
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#define RK806_SLEEP_CTR_SEL0 0x64
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#define RK806_SLEEP_CTR_SEL1 0x65
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#define RK806_SLEEP_CTR_SEL2 0x66
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#define RK806_SLEEP_CTR_SEL3 0x67
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#define RK806_SLEEP_CTR_SEL4 0x68
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#define RK806_SLEEP_CTR_SEL5 0x69
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#define RK806_DVS_CTRL_SEL0 0x6A
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#define RK806_DVS_CTRL_SEL1 0x6B
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#define RK806_DVS_CTRL_SEL2 0x6C
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#define RK806_DVS_CTRL_SEL3 0x6D
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#define RK806_DVS_CTRL_SEL4 0x6E
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#define RK806_DVS_CTRL_SEL5 0x6F
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#define RK806_DVS_START_CTRL 0x70
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#define RK806_SLEEP_GPIO 0x71
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#define RK806_SYS_CFG3 0x72
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#define RK806_ON_SOURCE 0x74
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#define RK806_OFF_SOURCE 0x75
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#define RK806_PWRON_KEY 0x76
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#define RK806_INT_STS0 0x77
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#define RK806_INT_MSK0 0x78
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#define RK806_INT_STS1 0x79
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#define RK806_INT_MSK1 0x7A
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#define RK806_GPIO_INT_CONFIG 0x7B
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#define RK806_DATA_REG0 0x7C
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#define RK806_DATA_REG1 0x7D
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#define RK806_DATA_REG2 0x7E
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#define RK806_DATA_REG3 0x7F
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#define RK806_DATA_REG4 0x80
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#define RK806_DATA_REG5 0x81
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#define RK806_DATA_REG6 0x82
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#define RK806_DATA_REG7 0x83
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#define RK806_DATA_REG8 0x84
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#define RK806_DATA_REG9 0x85
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#define RK806_DATA_REG10 0x86
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#define RK806_DATA_REG11 0x87
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#define RK806_DATA_REG12 0x88
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#define RK806_DATA_REG13 0x89
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#define RK806_DATA_REG14 0x8A
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#define RK806_DATA_REG15 0x8B
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#define RK806_TM_REG 0x8C
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#define RK806_OTP_EN_REG 0x8D
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#define RK806_FUNC_OTP_EN_REG 0x8E
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#define RK806_TEST_REG1 0x8F
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#define RK806_TEST_REG2 0x90
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#define RK806_TEST_REG3 0x91
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#define RK806_TEST_REG4 0x92
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#define RK806_TEST_REG5 0x93
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#define RK806_BUCK_VSEL_OTP_REG0 0x94
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#define RK806_BUCK_VSEL_OTP_REG1 0x95
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#define RK806_BUCK_VSEL_OTP_REG2 0x96
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#define RK806_BUCK_VSEL_OTP_REG3 0x97
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#define RK806_BUCK_VSEL_OTP_REG4 0x98
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#define RK806_BUCK_VSEL_OTP_REG5 0x99
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#define RK806_BUCK_VSEL_OTP_REG6 0x9A
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#define RK806_BUCK_VSEL_OTP_REG7 0x9B
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#define RK806_BUCK_VSEL_OTP_REG8 0x9C
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#define RK806_BUCK_VSEL_OTP_REG9 0x9D
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#define RK806_NLDO1_VSEL_OTP_REG0 0x9E
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#define RK806_NLDO1_VSEL_OTP_REG1 0x9F
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#define RK806_NLDO1_VSEL_OTP_REG2 0xA0
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#define RK806_NLDO1_VSEL_OTP_REG3 0xA1
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#define RK806_NLDO1_VSEL_OTP_REG4 0xA2
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#define RK806_PLDO_VSEL_OTP_REG0 0xA3
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#define RK806_PLDO_VSEL_OTP_REG1 0xA4
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#define RK806_PLDO_VSEL_OTP_REG2 0xA5
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#define RK806_PLDO_VSEL_OTP_REG3 0xA6
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#define RK806_PLDO_VSEL_OTP_REG4 0xA7
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#define RK806_PLDO_VSEL_OTP_REG5 0xA8
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#define RK806_BUCK_EN_OTP_REG1 0xA9
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#define RK806_NLDO_EN_OTP_REG1 0xAA
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#define RK806_PLDO_EN_OTP_REG1 0xAB
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#define RK806_BUCK_FB_RES_OTP_REG1 0xAC
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#define RK806_OTP_RESEV_REG0 0xAD
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#define RK806_OTP_RESEV_REG1 0xAE
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#define RK806_OTP_RESEV_REG2 0xAF
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#define RK806_OTP_RESEV_REG3 0xB0
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#define RK806_OTP_RESEV_REG4 0xB1
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#define RK806_BUCK_SEQ_REG0 0xB2
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#define RK806_BUCK_SEQ_REG1 0xB3
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#define RK806_BUCK_SEQ_REG2 0xB4
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#define RK806_BUCK_SEQ_REG3 0xB5
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#define RK806_BUCK_SEQ_REG4 0xB6
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#define RK806_BUCK_SEQ_REG5 0xB7
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#define RK806_BUCK_SEQ_REG6 0xB8
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#define RK806_BUCK_SEQ_REG7 0xB9
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#define RK806_BUCK_SEQ_REG8 0xBA
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#define RK806_BUCK_SEQ_REG9 0xBB
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#define RK806_BUCK_SEQ_REG10 0xBC
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#define RK806_BUCK_SEQ_REG11 0xBD
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#define RK806_BUCK_SEQ_REG12 0xBE
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#define RK806_BUCK_SEQ_REG13 0xBF
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#define RK806_BUCK_SEQ_REG14 0xC0
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#define RK806_BUCK_SEQ_REG15 0xC1
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#define RK806_BUCK_SEQ_REG16 0xC2
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#define RK806_BUCK_SEQ_REG17 0xC3
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#define RK806_HK_TRIM_REG1 0xC4
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#define RK806_HK_TRIM_REG2 0xC5
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#define RK806_BUCK_REF_TRIM_REG1 0xC6
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#define RK806_BUCK_REF_TRIM_REG2 0xC7
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#define RK806_BUCK_REF_TRIM_REG3 0xC8
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#define RK806_BUCK_REF_TRIM_REG4 0xC9
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#define RK806_BUCK_REF_TRIM_REG5 0xCA
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#define RK806_BUCK_OSC_TRIM_REG1 0xCB
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#define RK806_BUCK_OSC_TRIM_REG2 0xCC
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#define RK806_BUCK_OSC_TRIM_REG3 0xCD
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#define RK806_BUCK_OSC_TRIM_REG4 0xCE
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#define RK806_BUCK_OSC_TRIM_REG5 0xCF
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#define RK806_BUCK_TRIM_ZCDIOS_REG1 0xD0
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#define RK806_BUCK_TRIM_ZCDIOS_REG2 0xD1
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#define RK806_NLDO_TRIM_REG1 0xD2
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#define RK806_NLDO_TRIM_REG2 0xD3
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#define RK806_NLDO_TRIM_REG3 0xD4
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#define RK806_PLDO_TRIM_REG1 0xD5
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#define RK806_PLDO_TRIM_REG2 0xD6
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#define RK806_PLDO_TRIM_REG3 0xD7
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#define RK806_TRIM_ICOMP_REG1 0xD8
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#define RK806_TRIM_ICOMP_REG2 0xD9
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#define RK806_EFUSE_CONTROL_REGH 0xDA
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#define RK806_FUSE_PROG_REG 0xDB
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#define RK806_MAIN_FSM_STS_REG 0xDD
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#define RK806_FSM_REG 0xDE
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#define RK806_TOP_RESEV_OFFR 0xEC
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#define RK806_TOP_RESEV_POR 0xED
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#define RK806_BUCK_VRSN_REG1 0xEE
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#define RK806_BUCK_VRSN_REG2 0xEF
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#define RK806_NLDO_RLOAD_SEL_REG1 0xF0
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#define RK806_PLDO_RLOAD_SEL_REG1 0xF1
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#define RK806_PLDO_RLOAD_SEL_REG2 0xF2
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#define RK806_BUCK_CMIN_MX_REG1 0xF3
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#define RK806_BUCK_CMIN_MX_REG2 0xF4
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#define RK806_BUCK_FREQ_SET_REG1 0xF5
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#define RK806_BUCK_FREQ_SET_REG2 0xF6
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#define RK806_BUCK_RS_MEABS_REG1 0xF7
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#define RK806_BUCK_RS_MEABS_REG2 0xF8
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#define RK806_BUCK_RS_ZDLEB_REG1 0xF9
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#define RK806_BUCK_RS_ZDLEB_REG2 0xFA
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#define RK806_BUCK_RSERVE_REG1 0xFB
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#define RK806_BUCK_RSERVE_REG2 0xFC
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#define RK806_BUCK_RSERVE_REG3 0xFD
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#define RK806_BUCK_RSERVE_REG4 0xFE
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#define RK806_BUCK_RSERVE_REG5 0xFF
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/* INT_STS Register field definitions */
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#define RK806_INT_STS_PWRON_FALL BIT(0)
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#define RK806_INT_STS_PWRON_RISE BIT(1)
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#define RK806_INT_STS_PWRON BIT(2)
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#define RK806_INT_STS_PWRON_LP BIT(3)
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#define RK806_INT_STS_HOTDIE BIT(4)
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#define RK806_INT_STS_VDC_RISE BIT(5)
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#define RK806_INT_STS_VDC_FALL BIT(6)
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#define RK806_INT_STS_VB_LO BIT(7)
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#define RK806_INT_STS_REV0 BIT(0)
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#define RK806_INT_STS_REV1 BIT(1)
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#define RK806_INT_STS_REV2 BIT(2)
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#define RK806_INT_STS_CRC_ERROR BIT(3)
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#define RK806_INT_STS_SLP3_GPIO BIT(4)
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#define RK806_INT_STS_SLP2_GPIO BIT(5)
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#define RK806_INT_STS_SLP1_GPIO BIT(6)
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#define RK806_INT_STS_WDT BIT(7)
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/* spi command */
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#define RK806_CMD_READ 0
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#define RK806_CMD_WRITE BIT(7)
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#define RK806_CMD_CRC_EN BIT(6)
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#define RK806_CMD_CRC_DIS 0
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#define RK806_CMD_LEN_MSK 0x0f
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#define RK806_REG_H 0x00
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#define VERSION_AB 0x01
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enum rk806_reg_id {
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RK806_ID_DCDC1 = 0,
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RK806_ID_DCDC2,
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RK806_ID_DCDC3,
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RK806_ID_DCDC4,
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RK806_ID_DCDC5,
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RK806_ID_DCDC6,
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RK806_ID_DCDC7,
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RK806_ID_DCDC8,
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RK806_ID_DCDC9,
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RK806_ID_DCDC10,
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RK806_ID_NLDO1,
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RK806_ID_NLDO2,
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RK806_ID_NLDO3,
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RK806_ID_NLDO4,
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RK806_ID_NLDO5,
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RK806_ID_PLDO1,
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RK806_ID_PLDO2,
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RK806_ID_PLDO3,
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RK806_ID_PLDO4,
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RK806_ID_PLDO5,
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RK806_ID_PLDO6,
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RK806_ID_END,
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};
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/* Define the rk806 IRQ numbers */
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enum rk806_irqs {
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/* INT_STS0 registers */
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RK806_IRQ_PWRON_FALL,
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RK806_IRQ_PWRON_RISE,
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RK806_IRQ_PWRON,
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RK806_IRQ_PWRON_LP,
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RK806_IRQ_HOTDIE,
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RK806_IRQ_VDC_RISE,
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RK806_IRQ_VDC_FALL,
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RK806_IRQ_VB_LO,
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/* INT_STS0 registers */
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RK806_IRQ_REV0,
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RK806_IRQ_REV1,
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RK806_IRQ_REV2,
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RK806_IRQ_CRC_ERROR,
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RK806_IRQ_SLP3_GPIO,
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RK806_IRQ_SLP2_GPIO,
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RK806_IRQ_SLP1_GPIO,
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RK806_IRQ_WDT,
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};
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/* VCC1 low voltage threshold */
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enum rk806_lv_sel {
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VB_LO_SEL_2800,
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VB_LO_SEL_2900,
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VB_LO_SEL_3000,
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VB_LO_SEL_3100,
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VB_LO_SEL_3200,
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VB_LO_SEL_3300,
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VB_LO_SEL_3400,
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VB_LO_SEL_3500,
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};
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/* system shut down voltage select */
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enum rk806_uv_sel {
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VB_UV_SEL_2700,
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VB_UV_SEL_2800,
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VB_UV_SEL_2900,
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VB_UV_SEL_3000,
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VB_UV_SEL_3100,
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VB_UV_SEL_3200,
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VB_UV_SEL_3300,
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VB_UV_SEL_3400,
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};
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/* pin function */
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enum rk806_pwrctrl_fun {
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PWRCTRL_NULL_FUN,
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PWRCTRL_SLP_FUN,
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PWRCTRL_POWOFF_FUN,
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PWRCTRL_RST_FUN,
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PWRCTRL_DVS_FUN,
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PWRCTRL_GPIO_FUN,
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};
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/* pin pol */
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enum rk806_pin_level {
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POL_LOW,
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POL_HIGH,
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};
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enum rk806_vsel_ctr_sel {
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CTR_BY_NO_EFFECT,
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CTR_BY_PWRCTRL1,
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CTR_BY_PWRCTRL2,
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CTR_BY_PWRCTRL3,
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};
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enum rk806_dvs_ctr_sel {
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CTR_SEL_NO_EFFECT,
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CTR_SEL_DVS_START1,
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CTR_SEL_DVS_START2,
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CTR_SEL_DVS_START3,
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};
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enum rk806_pin_dr_sel {
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RK806_PIN_INPUT,
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RK806_PIN_OUTPUT,
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};
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enum rk806_int_pol {
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RK806_INT_POL_LOW,
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RK806_INT_POL_HIGH,
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};
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enum rk806_int_fun {
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RK806_INT_ONLY,
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RK806_INT_ADN_WKUP,
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};
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enum rk806_dvs_mode {
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RK806_DVS_NOT_SUPPORT,
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RK806_DVS_START1,
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RK806_DVS_START2,
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RK806_DVS_START3,
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RK806_DVS_PWRCTRL1,
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RK806_DVS_PWRCTRL2,
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RK806_DVS_PWRCTRL3,
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RK806_DVS_START_PWRCTR1,
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RK806_DVS_START_PWRCTR2,
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RK806_DVS_START_PWRCTR3,
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RK806_DVS_END,
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};
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enum rk806_fields {
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CHIP_NAME_H, CHIP_NAME_L, CHIP_VER, OTP_VER,
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POWER_EN0, POWER_EN1, POWER_EN2, POWER_EN3, POWER_EN4, POWER_EN5,
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BUCK4_EN_MASK, BUCK3_EN_MASK, BUCK2_EN_MASK, BUCK1_EN_MASK,
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BUCK4_EN, BUCK3_EN, BUCK2_EN, BUCK1_EN,
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BUCK8_EN_MASK, BUCK7_EN_MASK, BUCK6_EN_MASK, BUCK5_EN_MASK,
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BUCK8_EN, BUCK7_EN, BUCK6_EN, BUCK5_EN,
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BUCK10_EN_MASK, BUCK9_EN_MASK, BUCK10_EN, BUCK9_EN,
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NLDO4_EN_MASK, NLDO3_EN_MASK, NLDO2_EN_MASK, NLDO1_EN_MASK,
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NLDO4_EN, NLDO3_EN, NLDO2_EN, NLDO1_EN,
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PLDO4_EN_MASK, PLDO3_EN_MASK, PLDO2_EN_MASK, PLDO1_EN_MASK,
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PLDO4_EN, PLDO3_EN, PLDO2_EN, PLDO1_EN,
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NLDO5_EN_MASK, PLDO6_EN_MASK, PLDO5_EN_MASK,
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NLDO5_EN, PLDO6_EN, PLDO5_EN,
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BUCK8_SLP_EN, BUCK7_SLP_EN, BUCK6_SLP_EN, BUCK5_SLP_EN, BUCK4_SLP_EN,
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BUCK3_SLP_EN, BUCK2_SLP_EN, BUCK1_SLP_EN,
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BUCK10_SLP_EN, BUCK9_SLP_EN, NLDO5_SLP_EN, NLDO4_SLP_EN, NLDO3_SLP_EN,
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NLDO2_SLP_EN, NLDO1_SLP_EN,
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PLDO6_SLP_EN, PLDO5_SLP_EN, PLDO4_SLP_EN, PLDO3_SLP_EN,
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PLDO2_SLP_EN, PLDO1_SLP_EN,
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BUCK1_ON_VSEL, BUCK2_ON_VSEL, BUCK3_ON_VSEL, BUCK4_ON_VSEL, BUCK5_ON_VSEL,
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BUCK6_ON_VSEL, BUCK7_ON_VSEL, BUCK8_ON_VSEL, BUCK9_ON_VSEL, BUCK10_ON_VSEL,
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BUCK1_SLP_VSEL, BUCK2_SLP_VSEL, BUCK3_SLP_VSEL, BUCK4_SLP_VSEL, BUCK5_SLP_VSEL,
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BUCK6_SLP_VSEL, BUCK7_SLP_VSEL, BUCK8_SLP_VSEL, BUCK9_SLP_VSEL, BUCK10_SLP_VSEL,
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NLDO1_ON_VSEL, NLDO2_ON_VSEL, NLDO3_ON_VSEL, NLDO4_ON_VSEL, NLDO5_ON_VSEL,
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NLDO1_SLP_VSEL, NLDO2_SLP_VSEL, NLDO3_SLP_VSEL, NLDO4_SLP_VSEL, NLDO5_SLP_VSEL,
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PLDO1_ON_VSEL, PLDO2_ON_VSEL, PLDO3_ON_VSEL, PLDO4_ON_VSEL, PLDO5_ON_VSEL,
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PLDO6_ON_VSEL,
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PLDO1_SLP_VSEL, PLDO2_SLP_VSEL, PLDO3_SLP_VSEL, PLDO4_SLP_VSEL, PLDO5_SLP_VSEL,
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PLDO6_SLP_VSEL,
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BUCK1_RATE, BUCK2_RATE, BUCK3_RATE, BUCK4_RATE, BUCK5_RATE, BUCK6_RATE,
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BUCK7_RATE, BUCK8_RATE, BUCK9_RATE, BUCK10_RATE,
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PWRON_STS, VDC_STS, VB_UV_STSS, VB_LO_STS, HOTDIE_STS, TSD_STS, VB_OV_STS,
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VB_UV_DLY, VB_UV_SEL, VB_LO_ACT, VB_LO_SEL,
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ABNORDET_EN, TSD_TEMP, HOTDIE_TMP, SYS_OV_SD_EN, SYS_OV_SD_DLY_SEL, DLY_ABN_SHORT,
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VCCXDET_DIS, OSC_TC, ENB2_2M, ENB_32K,
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PWRCTRL1_FUN, PWRCTRL2_FUN, PWRCTRL3_FUN,
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PWRCTRL1_POL, PWRCTRL2_POL, PWRCTRL3_POL,
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BUCK1_VSEL_CTR_SEL, BUCK2_VSEL_CTR_SEL, BUCK3_VSEL_CTR_SEL, BUCK4_VSEL_CTR_SEL,
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BUCK5_VSEL_CTR_SEL, BUCK6_VSEL_CTR_SEL, BUCK7_VSEL_CTR_SEL, BUCK8_VSEL_CTR_SEL,
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BUCK9_VSEL_CTR_SEL, BUCK10_VSEL_CTR_SEL,
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NLDO1_VSEL_CTR_SEL, NLDO2_VSEL_CTR_SEL, NLDO3_VSEL_CTR_SEL, NLDO4_VSEL_CTR_SEL,
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NLDO5_VSEL_CTR_SEL,
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PLDO1_VSEL_CTR_SEL, PLDO2_VSEL_CTR_SEL, PLDO3_VSEL_CTR_SEL, PLDO4_VSEL_CTR_SEL,
|
PLDO5_VSEL_CTR_SEL, PLDO6_VSEL_CTR_SEL,
|
BUCK1_DVS_CTR_SEL, BUCK2_DVS_CTR_SEL, BUCK3_DVS_CTR_SEL, BUCK4_DVS_CTR_SEL,
|
BUCK5_DVS_CTR_SEL, BUCK6_DVS_CTR_SEL, BUCK7_DVS_CTR_SEL, BUCK8_DVS_CTR_SEL,
|
BUCK9_DVS_CTR_SEL, BUCK10_DVS_CTR_SEL,
|
NLDO1_DVS_CTR_SEL, NLDO2_DVS_CTR_SEL, NLDO3_DVS_CTR_SEL, NLDO4_DVS_CTR_SEL,
|
NLDO5_DVS_CTR_SEL,
|
PLDO1_DVS_CTR_SEL, PLDO2_DVS_CTR_SEL, PLDO3_DVS_CTR_SEL, PLDO4_DVS_CTR_SEL,
|
PLDO5_DVS_CTR_SEL, PLDO6_DVS_CTR_SEL,
|
DVS_START1, DVS_START2, DVS_START3,
|
SLP3_DATA, SLP2_DATA, SLP1_DATA, SLP3_DR, SLP2_DR, SLP1_DR,
|
|
RST_FUN, DEV_RST, DEV_SLP, SLAVE_RESTART_FUN, DEV_OFF,
|
WDT_CLR, WDT_EN, WDT_SET, ON_SOURCE, OFF_SOURCE,
|
ON_PWRON, ON_VDC, RESTART_RESETB, RESTART_PWRON_LP, RESTART_SLP,
|
RESTART_DEV_RST, RESTART_WDT,
|
OFF_SLP, VB_SYS_OV, OFF_TSD, OFF_DEV_OFF, OFF_PWRON_LP, OFF_VB_LO,
|
PWRON_ON_TIME, PWRON_LP_ACT, PWRON_LP_OFF_TIME, PWRON_LP_TM_SEL, PWRON_DB_SEL,
|
VB_LO_INT, VDC_FALL_INT, VDC_RISE_INT, HOTDIE_INT, PWRON_LP_INT, PWRON_INT,
|
PWRON_RISE_INT, PWRON_FALL_INT,
|
VB_LO_IM, VDC_FALL_INT_IM, VDC_RISE_IM, HOTDIE_IM, PWRON_LP_IM,
|
PWRON_IM, PWRON_RISE_INT_IM, PWRON_FALL_INT_IM,
|
WDT_INT, SLP1_GPIO_INT, SLP2_GPIO_INT, SLP3_GPIO_INT,
|
WDT_INT_IM, SLP1_GPIO_IM, SLP2_GPIO_IM, SLP3_GPIO_IM,
|
INT_FUNCTION, INT_POL, INT_FC_EN,
|
LDO_RATE, BUCK1_RATE2, BUCK2_RATE2, BUCK3_RATE2, BUCK4_RATE2,
|
BUCK5_RATE2, BUCK6_RATE2, BUCK7_RATE2, BUCK8_RATE2, BUCK9_RATE2,
|
BUCK10_RATE2,
|
F_MAX_FIELDS
|
};
|
|
struct rk806_platform_data {
|
int low_voltage_threshold;
|
int shutdown_voltage_threshold;
|
int force_shutdown_enable;
|
int shutdown_temperture_threshold;
|
int hotdie_temperture_threshold;
|
};
|
|
struct rk806_pin_info {
|
struct pinctrl *p;
|
struct pinctrl_state *default_st;
|
struct pinctrl_state *power_off;
|
struct pinctrl_state *reset;
|
struct pinctrl_state *sleep;
|
struct pinctrl_state *dvs;
|
};
|
|
/*
|
* struct rk806 - state holder for the rk806 driver
|
*
|
* Device data may be used to access the rk806 chip
|
*/
|
struct rk806 {
|
struct device *dev;
|
struct regmap *regmap;
|
struct regmap_field *rmap_fields[F_MAX_FIELDS];
|
/* IRQ Data */
|
int irq;
|
struct regmap_irq_chip_data *irq_data;
|
struct rk806_platform_data *pdata;
|
struct rk806_pin_info *pins;
|
int vb_lo_irq;
|
};
|
|
extern const struct regmap_config rk806_regmap_config_spi;
|
int rk806_device_init(struct rk806 *rk806);
|
int rk806_device_exit(struct rk806 *rk806);
|
int rk806_field_write(struct rk806 *rk806,
|
enum rk806_fields field_id,
|
unsigned int val);
|
int rk806_field_read(struct rk806 *rk806,
|
enum rk806_fields field_id);
|
#endif /* __LINUX_REGULATOR_RK806_H */
|
