/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __SPARC_SWITCH_TO_H
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#define __SPARC_SWITCH_TO_H
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#include <asm/smp.h>
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extern struct thread_info *current_set[NR_CPUS];
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/*
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* Flush windows so that the VM switch which follows
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* would not pull the stack from under us.
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*
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* SWITCH_ENTER and SWITCH_DO_LAZY_FPU do not work yet (e.g. SMP does not work)
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* XXX WTF is the above comment? Found in late teen 2.4.x.
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*/
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#ifdef CONFIG_SMP
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#define SWITCH_ENTER(prv) \
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do { \
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if (test_tsk_thread_flag(prv, TIF_USEDFPU)) { \
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put_psr(get_psr() | PSR_EF); \
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fpsave(&(prv)->thread.float_regs[0], &(prv)->thread.fsr, \
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&(prv)->thread.fpqueue[0], &(prv)->thread.fpqdepth); \
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clear_tsk_thread_flag(prv, TIF_USEDFPU); \
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(prv)->thread.kregs->psr &= ~PSR_EF; \
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} \
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} while(0)
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#define SWITCH_DO_LAZY_FPU(next) /* */
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#else
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#define SWITCH_ENTER(prv) /* */
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#define SWITCH_DO_LAZY_FPU(nxt) \
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do { \
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if (last_task_used_math != (nxt)) \
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(nxt)->thread.kregs->psr&=~PSR_EF; \
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} while(0)
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#endif
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#define prepare_arch_switch(next) do { \
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__asm__ __volatile__( \
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".globl\tflush_patch_switch\nflush_patch_switch:\n\t" \
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"save %sp, -0x40, %sp; save %sp, -0x40, %sp; save %sp, -0x40, %sp\n\t" \
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"save %sp, -0x40, %sp; save %sp, -0x40, %sp; save %sp, -0x40, %sp\n\t" \
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"save %sp, -0x40, %sp\n\t" \
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"restore; restore; restore; restore; restore; restore; restore"); \
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} while(0)
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/* Much care has gone into this code, do not touch it.
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*
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* We need to loadup regs l0/l1 for the newly forked child
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* case because the trap return path relies on those registers
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* holding certain values, gcc is told that they are clobbered.
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* Gcc needs registers for 3 values in and 1 value out, so we
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* clobber every non-fixed-usage register besides l2/l3/o4/o5. -DaveM
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*
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* Hey Dave, that do not touch sign is too much of an incentive
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* - Anton & Pete
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*/
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#define switch_to(prev, next, last) do { \
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SWITCH_ENTER(prev); \
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SWITCH_DO_LAZY_FPU(next); \
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cpumask_set_cpu(smp_processor_id(), mm_cpumask(next->active_mm)); \
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__asm__ __volatile__( \
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"sethi %%hi(here - 0x8), %%o7\n\t" \
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"mov %%g6, %%g3\n\t" \
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"or %%o7, %%lo(here - 0x8), %%o7\n\t" \
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"rd %%psr, %%g4\n\t" \
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"std %%sp, [%%g6 + %4]\n\t" \
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"rd %%wim, %%g5\n\t" \
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"wr %%g4, 0x20, %%psr\n\t" \
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"nop\n\t" \
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"std %%g4, [%%g6 + %3]\n\t" \
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"ldd [%2 + %3], %%g4\n\t" \
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"mov %2, %%g6\n\t" \
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".globl patchme_store_new_current\n" \
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"patchme_store_new_current:\n\t" \
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"st %2, [%1]\n\t" \
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"wr %%g4, 0x20, %%psr\n\t" \
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"nop\n\t" \
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"nop\n\t" \
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"nop\n\t" /* LEON needs all 3 nops: load to %sp depends on CWP. */ \
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"ldd [%%g6 + %4], %%sp\n\t" \
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"wr %%g5, 0x0, %%wim\n\t" \
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"ldd [%%sp + 0x00], %%l0\n\t" \
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"ldd [%%sp + 0x38], %%i6\n\t" \
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"wr %%g4, 0x0, %%psr\n\t" \
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"nop\n\t" \
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"nop\n\t" \
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"jmpl %%o7 + 0x8, %%g0\n\t" \
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" ld [%%g3 + %5], %0\n\t" \
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"here:\n" \
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: "=&r" (last) \
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: "r" (&(current_set[hard_smp_processor_id()])), \
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"r" (task_thread_info(next)), \
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"i" (TI_KPSR), \
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"i" (TI_KSP), \
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"i" (TI_TASK) \
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: "g1", "g2", "g3", "g4", "g5", "g7", \
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"l0", "l1", "l3", "l4", "l5", "l6", "l7", \
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"i0", "i1", "i2", "i3", "i4", "i5", \
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"o0", "o1", "o2", "o3", "o7"); \
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} while(0)
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void fpsave(unsigned long *fpregs, unsigned long *fsr,
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void *fpqueue, unsigned long *fpqdepth);
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void synchronize_user_stack(void);
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#endif /* __SPARC_SWITCH_TO_H */
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