// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
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*
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*/
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/ {
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aliases {
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mmc0 = &sdhci;
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mmc1 = &sdmmc;
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mmc2 = &sdio;
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};
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chosen: chosen {
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bootargs = "earlycon=uart8250,mmio32,0xfeb50000 console=ttyFIQ0 irqchip.gicv3_pseudo_nmi=0 root=PARTUUID=614e0000-0000 rw rootwait net.ifnames=0";
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};
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cspmu: cspmu@fd10c000 {
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compatible = "rockchip,cspmu";
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reg = <0x0 0xfd10c000 0x0 0x1000>,
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<0x0 0xfd10d000 0x0 0x1000>,
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<0x0 0xfd10e000 0x0 0x1000>,
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<0x0 0xfd10f000 0x0 0x1000>,
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<0x0 0xfd12c000 0x0 0x1000>,
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<0x0 0xfd12d000 0x0 0x1000>,
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<0x0 0xfd12e000 0x0 0x1000>,
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<0x0 0xfd12f000 0x0 0x1000>;
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};
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debug: debug@fd104000 {
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compatible = "rockchip,debug";
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reg = <0x0 0xfd104000 0x0 0x1000>,
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<0x0 0xfd105000 0x0 0x1000>,
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<0x0 0xfd106000 0x0 0x1000>,
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<0x0 0xfd107000 0x0 0x1000>,
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<0x0 0xfd124000 0x0 0x1000>,
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<0x0 0xfd125000 0x0 0x1000>,
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<0x0 0xfd126000 0x0 0x1000>,
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<0x0 0xfd127000 0x0 0x1000>;
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};
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fiq_debugger: fiq-debugger {
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compatible = "rockchip,fiq-debugger";
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rockchip,serial-id = <2>;
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rockchip,wake-irq = <0>;
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/* If enable uart uses irq instead of fiq */
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rockchip,irq-mode-enable = <1>;
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rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */
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interrupts = <GIC_SPI 423 IRQ_TYPE_LEVEL_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart2m0_xfer>;
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status = "okay";
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};
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firmware {
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optee: optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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//status = "disabled";
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};
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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cma {
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compatible = "shared-dma-pool";
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reusable;
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size = <0x0 (8 * 0x100000)>;
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linux,cma-default;
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};
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drm_logo: drm-logo@00000000 {
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compatible = "rockchip,drm-logo";
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reg = <0x0 0x0 0x0 0x0>;
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};
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drm_cubic_lut: drm-cubic-lut@00000000 {
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compatible = "rockchip,drm-cubic-lut";
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reg = <0x0 0x0 0x0 0x0>;
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};
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ramoops: ramoops@110000 {
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compatible = "ramoops";
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reg = <0x0 0x110000 0x0 0xf0000>;
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record-size = <0x20000>;
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console-size = <0x80000>;
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ftrace-size = <0x00000>;
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pmsg-size = <0x50000>;
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};
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};
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};
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&display_subsystem {
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memory-region = <&drm_logo>;
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memory-region-names = "drm-logo";
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};
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&dfi {
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status = "okay";
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};
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&dmc {
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status = "okay";
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center-supply = <&vdd_ddr_s0>;
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mem-supply = <&vdd_log_s0>;
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};
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&rng {
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status = "okay";
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};
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