/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
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/*
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* Microsemi Ocelot Switch driver
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*
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* License: Dual MIT/GPL
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* Copyright (c) 2017 Microsemi Corporation
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* Copyright 2020 NXP
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*/
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#ifndef _MSCC_OCELOT_PTP_H_
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#define _MSCC_OCELOT_PTP_H_
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#include <linux/ptp_clock_kernel.h>
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#include <soc/mscc/ocelot.h>
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#define PTP_PIN_CFG_RSZ 0x20
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#define PTP_PIN_TOD_SEC_MSB_RSZ PTP_PIN_CFG_RSZ
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#define PTP_PIN_TOD_SEC_LSB_RSZ PTP_PIN_CFG_RSZ
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#define PTP_PIN_TOD_NSEC_RSZ PTP_PIN_CFG_RSZ
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#define PTP_PIN_WF_HIGH_PERIOD_RSZ PTP_PIN_CFG_RSZ
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#define PTP_PIN_WF_LOW_PERIOD_RSZ PTP_PIN_CFG_RSZ
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#define PTP_PIN_CFG_DOM BIT(0)
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#define PTP_PIN_CFG_SYNC BIT(2)
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#define PTP_PIN_CFG_ACTION(x) ((x) << 3)
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#define PTP_PIN_CFG_ACTION_MASK PTP_PIN_CFG_ACTION(0x7)
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enum {
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PTP_PIN_ACTION_IDLE = 0,
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PTP_PIN_ACTION_LOAD,
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PTP_PIN_ACTION_SAVE,
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PTP_PIN_ACTION_CLOCK,
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PTP_PIN_ACTION_DELTA,
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PTP_PIN_ACTION_NOSYNC,
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PTP_PIN_ACTION_SYNC,
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};
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#define PTP_CFG_MISC_PTP_EN BIT(2)
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#define PSEC_PER_SEC 1000000000000LL
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#define PTP_CFG_CLK_ADJ_CFG_ENA BIT(0)
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#define PTP_CFG_CLK_ADJ_CFG_DIR BIT(1)
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#define PTP_CFG_CLK_ADJ_FREQ_NS BIT(30)
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int ocelot_ptp_gettime64(struct ptp_clock_info *ptp, struct timespec64 *ts);
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int ocelot_ptp_settime64(struct ptp_clock_info *ptp,
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const struct timespec64 *ts);
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int ocelot_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta);
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int ocelot_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm);
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int ocelot_ptp_verify(struct ptp_clock_info *ptp, unsigned int pin,
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enum ptp_pin_function func, unsigned int chan);
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int ocelot_ptp_enable(struct ptp_clock_info *ptp,
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struct ptp_clock_request *rq, int on);
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int ocelot_init_timestamp(struct ocelot *ocelot,
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const struct ptp_clock_info *info);
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int ocelot_deinit_timestamp(struct ocelot *ocelot);
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#endif
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