/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2006 Thomas Gleixner <tglx@linutronix.de>
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*
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* Info:
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* Contains defines, datastructures for ndfc nand controller
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*/
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#ifndef __LINUX_MTD_NDFC_H
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#define __LINUX_MTD_NDFC_H
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/* NDFC Register definitions */
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#define NDFC_CMD 0x00
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#define NDFC_ALE 0x04
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#define NDFC_DATA 0x08
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#define NDFC_ECC 0x10
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#define NDFC_BCFG0 0x30
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#define NDFC_BCFG1 0x34
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#define NDFC_BCFG2 0x38
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#define NDFC_BCFG3 0x3c
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#define NDFC_CCR 0x40
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#define NDFC_STAT 0x44
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#define NDFC_HWCTL 0x48
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#define NDFC_REVID 0x50
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#define NDFC_STAT_IS_READY 0x01000000
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#define NDFC_CCR_RESET_CE 0x80000000 /* CE Reset */
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#define NDFC_CCR_RESET_ECC 0x40000000 /* ECC Reset */
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#define NDFC_CCR_RIE 0x20000000 /* Interrupt Enable on Device Rdy */
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#define NDFC_CCR_REN 0x10000000 /* Enable wait for Rdy in LinearR */
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#define NDFC_CCR_ROMEN 0x08000000 /* Enable ROM In LinearR */
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#define NDFC_CCR_ARE 0x04000000 /* Auto-Read Enable */
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#define NDFC_CCR_BS(x) (((x) & 0x3) << 24) /* Select Bank on CE[x] */
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#define NDFC_CCR_BS_MASK 0x03000000 /* Select Bank */
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#define NDFC_CCR_ARAC0 0x00000000 /* 3 Addr, 1 Col 2 Row 512b page */
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#define NDFC_CCR_ARAC1 0x00001000 /* 4 Addr, 1 Col 3 Row 512b page */
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#define NDFC_CCR_ARAC2 0x00002000 /* 4 Addr, 2 Col 2 Row 2K page */
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#define NDFC_CCR_ARAC3 0x00003000 /* 5 Addr, 2 Col 3 Row 2K page */
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#define NDFC_CCR_ARAC_MASK 0x00003000 /* Auto-Read mode Addr Cycles */
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#define NDFC_CCR_RPG 0x0000C000 /* Auto-Read Page */
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#define NDFC_CCR_EBCC 0x00000004 /* EBC Configuration Completed */
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#define NDFC_CCR_DHC 0x00000002 /* Direct Hardware Control Enable */
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#define NDFC_BxCFG_EN 0x80000000 /* Bank Enable */
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#define NDFC_BxCFG_CED 0x40000000 /* nCE Style */
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#define NDFC_BxCFG_SZ_MASK 0x08000000 /* Bank Size */
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#define NDFC_BxCFG_SZ_8BIT 0x00000000 /* 8bit */
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#define NDFC_BxCFG_SZ_16BIT 0x08000000 /* 16bit */
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#define NDFC_MAX_BANKS 4
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struct ndfc_controller_settings {
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uint32_t ccr_settings;
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uint64_t ndfc_erpn;
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};
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struct ndfc_chip_settings {
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uint32_t bank_settings;
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};
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#endif
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