/*
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* (C) Copyright 2010
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* Eastman Kodak Company, <www.kodak.com>
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* Michael Zaidman, <michael.zaidman@kodak.com>
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*
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* The code is based on the cpu/mpc83xx/ecc.c written by
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* Dave Liu <daveliu@freescale.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <mpc83xx.h>
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#include <watchdog.h>
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#include <asm/io.h>
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#include <post.h>
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#if CONFIG_POST & CONFIG_SYS_POST_ECC
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/*
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* We use the RAW I/O accessors where possible in order to
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* achieve performance goal, since the test's execution time
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* affects the board start up time.
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*/
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static inline void ecc_clear(ddr83xx_t *ddr)
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{
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/* Clear capture registers */
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__raw_writel(0, &ddr->capture_address);
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__raw_writel(0, &ddr->capture_data_hi);
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__raw_writel(0, &ddr->capture_data_lo);
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__raw_writel(0, &ddr->capture_ecc);
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__raw_writel(0, &ddr->capture_attributes);
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/* Clear SBEC and set SBET to 1 */
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out_be32(&ddr->err_sbe, 1 << ECC_ERROR_MAN_SBET_SHIFT);
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/* Clear Error Detect register */
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out_be32(&ddr->err_detect, ECC_ERROR_DETECT_MME |\
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ECC_ERROR_DETECT_MBE |\
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ECC_ERROR_DETECT_SBE |\
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ECC_ERROR_DETECT_MSE);
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isync();
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}
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int ecc_post_test(int flags)
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{
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int ret = 0;
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int int_state;
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int errbit;
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u32 pattern[2], writeback[2], retval[2];
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ddr83xx_t *ddr = &((immap_t *)CONFIG_SYS_IMMR)->ddr;
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volatile u64 *addr = (u64 *)CONFIG_SYS_POST_ECC_START_ADDR;
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/* The pattern is written into memory to generate error */
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pattern[0] = 0xfedcba98UL;
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pattern[1] = 0x76543210UL;
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/* After injecting error, re-initialize the memory with the value */
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writeback[0] = ~pattern[0];
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writeback[1] = ~pattern[1];
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/* Check if ECC is enabled */
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if (__raw_readl(&ddr->err_disable) & ECC_ERROR_ENABLE) {
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debug("DDR's ECC is not enabled, skipping the ECC POST.\n");
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return 0;
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}
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int_state = disable_interrupts();
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icache_enable();
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#ifdef CONFIG_DDR_32BIT
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/* It seems like no one really uses the CONFIG_DDR_32BIT mode */
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#error "Add ECC POST support for CONFIG_DDR_32BIT here!"
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#else
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for (addr = (u64*)CONFIG_SYS_POST_ECC_START_ADDR, errbit=0;
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addr < (u64*)CONFIG_SYS_POST_ECC_STOP_ADDR; addr++, errbit++ ) {
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WATCHDOG_RESET();
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ecc_clear(ddr);
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/* Enable error injection */
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setbits_be32(&ddr->ecc_err_inject, ECC_ERR_INJECT_EIEN);
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sync();
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isync();
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/* Set bit to be injected */
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if (errbit < 32) {
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__raw_writel(1 << errbit, &ddr->data_err_inject_lo);
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__raw_writel(0, &ddr->data_err_inject_hi);
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} else {
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__raw_writel(0, &ddr->data_err_inject_lo);
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__raw_writel(1<<(errbit-32), &ddr->data_err_inject_hi);
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}
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sync();
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isync();
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/* Write memory location injecting SBE */
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ppcDWstore((u32*)addr, pattern);
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sync();
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/* Disable error injection */
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clrbits_be32(&ddr->ecc_err_inject, ECC_ERR_INJECT_EIEN);
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sync();
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isync();
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/* Data read should generate SBE */
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ppcDWload((u32*)addr, retval);
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sync();
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if (!(__raw_readl(&ddr->err_detect) & ECC_ERROR_DETECT_SBE) ||
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(__raw_readl(&ddr->data_err_inject_hi) !=
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(__raw_readl(&ddr->capture_data_hi) ^ pattern[0])) ||
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(__raw_readl(&ddr->data_err_inject_lo) !=
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(__raw_readl(&ddr->capture_data_lo) ^ pattern[1]))) {
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post_log("ECC failed to detect SBE error at %08x, "
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"SBE injection mask %08x-%08x, wrote "
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"%08x-%08x, read %08x-%08x\n", addr,
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ddr->data_err_inject_hi,
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ddr->data_err_inject_lo,
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pattern[0], pattern[1],
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retval[0], retval[1]);
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printf("ERR_DETECT Reg: %08x\n", ddr->err_detect);
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printf("ECC CAPTURE_DATA Reg: %08x-%08x\n",
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ddr->capture_data_hi, ddr->capture_data_lo);
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ret = 1;
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break;
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}
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/* Re-initialize the ECC memory */
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ppcDWstore((u32*)addr, writeback);
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sync();
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isync();
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errbit %= 63;
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}
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#endif /* !CONFIG_DDR_32BIT */
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ecc_clear(ddr);
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icache_disable();
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if (int_state)
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enable_interrupts();
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return ret;
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}
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#endif
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