/*
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* Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <linux/compat.h>
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#include <linux/delay.h>
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#include "flash.h"
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#include "flash_com.h"
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#include "nandc.h"
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#include "rk_sftl.h"
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#define CPU_DELAY_NS(n) ndelay(n)
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#define usleep_range(a, b) udelay((b))
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#define NANDC_MASTER_EN
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void __iomem *nandc_base;
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static u8 g_nandc_ver;
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static u32 g_nandc_ecc_bits;
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#ifdef NANDC_MASTER_EN
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static struct MASTER_INFO_T master;
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static u32 *g_master_temp_buf;
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#endif
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u8 nandc_get_version(void)
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{
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return g_nandc_ver;
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}
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void nandc_init(void __iomem *nandc_addr)
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{
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union FM_CTL_T ctl_reg;
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nandc_base = nandc_addr;
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ctl_reg.d32 = 0;
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g_nandc_ver = 6;
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if (nandc_readl(NANDC_V9_NANDC_VER) == RK3326_NANDC_VER)
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g_nandc_ver = 9;
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if (g_nandc_ver == 9) {
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ctl_reg.V9.wp = 1;
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ctl_reg.V9.sif_read_delay = 2;
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nandc_writel(ctl_reg.d32, NANDC_V9_FMCTL);
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nandc_writel(0, NANDC_V9_RANDMZ_CFG);
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nandc_writel(0x1041, NANDC_V9_FMWAIT);
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} else {
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ctl_reg.V6.wp = 1;
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nandc_writel(ctl_reg.d32, NANDC_FMCTL);
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nandc_writel(0, NANDC_RANDMZ_CFG);
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nandc_writel(0x1061, NANDC_FMWAIT);
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}
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nandc_time_cfg(40);
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#ifdef NANDC_MASTER_EN
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if (!g_master_temp_buf)
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g_master_temp_buf = (u32 *)ftl_malloc(MAX_FLASH_PAGE_SIZE +
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MAX_FLASH_PAGE_SIZE / 8);
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master.page_buf = &g_master_temp_buf[0];
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master.spare_buf = &g_master_temp_buf[MAX_FLASH_PAGE_SIZE / 4];
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master.mapped = 0;
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#endif
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}
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void nandc_flash_cs(u8 chip_sel)
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{
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union FM_CTL_T tmp;
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tmp.d32 = nandc_readl(NANDC_FMCTL);
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tmp.V6.cs = 0x01 << chip_sel;
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nandc_writel(tmp.d32, NANDC_FMCTL);
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}
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void nandc_flash_de_cs(u8 chip_sel)
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{
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union FM_CTL_T tmp;
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tmp.d32 = nandc_readl(NANDC_FMCTL);
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tmp.V6.cs = 0;
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tmp.V6.flash_abort_clear = 0;
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nandc_writel(tmp.d32, NANDC_FMCTL);
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}
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u32 nandc_delayns(u32 count)
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{
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CPU_DELAY_NS(count);
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return 0;
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}
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u32 nandc_wait_flash_ready(u8 chip_sel)
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{
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union FM_CTL_T tmp;
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u32 status;
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u32 i;
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status = 0;
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for (i = 0; i < 100000; i++) {
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nandc_delayns(100);
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tmp.d32 = nandc_readl(NANDC_FMCTL);
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if (tmp.V6.rdy != 0)
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break;
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}
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if (i >= 100000)
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status = -1;
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return status;
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}
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void nandc_randmz_sel(u8 chip_sel, u32 randmz_seed)
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{
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nandc_writel(randmz_seed, NANDC_RANDMZ_CFG);
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}
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void nandc_time_cfg(u32 ns)
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{
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if (g_nandc_ver == 9) {
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if (ns < 36)
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nandc_writel(0x1041, NANDC_V9_FMWAIT);
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else if (ns >= 100)
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nandc_writel(0x2082, NANDC_V9_FMWAIT);
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else
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nandc_writel(0x1061, NANDC_V9_FMWAIT);
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} else {
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if (ns < 36)
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nandc_writel(0x1061, NANDC_FMWAIT);
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else if (ns >= 100)
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nandc_writel(0x2082, NANDC_FMWAIT);
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else
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nandc_writel(0x1081, NANDC_FMWAIT);
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}
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}
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void nandc_bch_sel(u8 bits)
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{
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union BCH_CTL_T tmp;
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union FL_CTL_T fl_reg;
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u8 bch_config;
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fl_reg.d32 = 0;
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fl_reg.V6.rst = 1;
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g_nandc_ecc_bits = bits;
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if (g_nandc_ver == 9) {
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nandc_writel(fl_reg.d32, NANDC_V9_FLCTL);
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if (bits == 70)
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bch_config = 0;
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else if (bits == 60)
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bch_config = 3;
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else if (bits == 40)
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bch_config = 2;
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else
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bch_config = 1;
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tmp.d32 = 0;
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tmp.V9.bchmode = bch_config;
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tmp.V9.bchrst = 1;
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nandc_writel(tmp.d32, NANDC_V9_BCHCTL);
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} else {
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nandc_writel(fl_reg.d32, NANDC_FLCTL);
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tmp.d32 = 0;
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tmp.V6.addr = 0x10;
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tmp.V6.bch_mode1 = 0;
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if (bits == 16) {
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tmp.V6.bch_mode = 0;
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} else if (bits == 24) {
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tmp.V6.bch_mode = 1;
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} else {
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tmp.V6.bch_mode1 = 1;
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tmp.V6.bch_mode = 1;
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if (bits == 40)
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tmp.V6.bch_mode = 0;
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}
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tmp.V6.rst = 1;
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nandc_writel(tmp.d32, NANDC_BCHCTL);
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}
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}
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/*
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*Nandc xfer data transmission
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*1. set bch register except nandc version equals 9
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*2. set internal transfer control register
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*3. set bus transfer
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* a. target memory data address
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* b. ahb setting
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*4. configure register orderly and start transmission
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*/
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static void nandc_xfer_start(u8 dir, u8 n_sec, u32 *data, u32 *spare)
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{
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union BCH_CTL_T bch_reg;
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union FL_CTL_T fl_reg;
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u32 i;
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union MTRANS_CFG_T master_reg;
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u16 *p_spare_tmp = (u16 *)spare;
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unsigned long vir_addr;
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fl_reg.d32 = 0;
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if (g_nandc_ver == 9) {
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fl_reg.V9.flash_rdn = dir;
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fl_reg.V9.bypass = 1;
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fl_reg.V9.tr_count = 1;
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fl_reg.V9.async_tog_mix = 1;
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fl_reg.V9.cor_able = 1;
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fl_reg.V9.st_addr = 0;
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fl_reg.V9.page_num = (n_sec + 1) / 2;
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/* dma start transfer data do care flash rdy */
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fl_reg.V9.flash_st_mod = 1;
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if (dir != 0) {
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for (i = 0; i < n_sec / 2; i++) {
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if (spare) {
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master.spare_buf[i] =
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(p_spare_tmp[0]) |
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((u32)p_spare_tmp[1] << 16);
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p_spare_tmp += 2;
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} else {
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master.spare_buf[i] = 0xffffffff;
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}
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}
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} else {
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master.spare_buf[0] = 1;
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}
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master.page_vir = (u32 *)((data == (u32 *)NULL) ?
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master.page_buf :
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(u32 *)data);
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master.spare_vir = (u32 *)master.spare_buf;
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master.page_phy = (u32)((unsigned long)master.page_vir);
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master.spare_phy = (u32)((unsigned long)master.spare_vir);
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vir_addr = ((unsigned long)master.page_phy);
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flush_dcache_range(vir_addr & (~0x3FuL),
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((vir_addr + 63) & (~0x3FuL)) +
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fl_reg.V6.page_num * 1024);
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vir_addr = ((unsigned long)master.spare_phy);
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flush_dcache_range(vir_addr & (~0x3FuL),
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((vir_addr + 63) & (~0x3FuL)) +
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fl_reg.V6.page_num * 128);
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master.mapped = 1;
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nandc_writel(master.page_phy, NANDC_V9_MTRANS_SADDR0);
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nandc_writel(master.spare_phy, NANDC_V9_MTRANS_SADDR1);
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master_reg.d32 = nandc_readl(NANDC_V9_MTRANS_CFG);
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master_reg.V9.incr_num = 16;
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master_reg.V9.burst = 7;
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master_reg.V9.hsize = 2;
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master_reg.V9.bus_mode = 1;
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master_reg.V9.ahb_wr = !dir;
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master_reg.V9.ahb_wr_st = 1;
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master_reg.V9.redundance_size = 0;
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nandc_writel(master_reg.d32, NANDC_V9_MTRANS_CFG);
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nandc_writel(fl_reg.d32, NANDC_V9_FLCTL);
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fl_reg.V9.flash_st = 1;
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nandc_writel(fl_reg.d32, NANDC_V9_FLCTL);
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} else {
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bch_reg.d32 = nandc_readl(NANDC_BCHCTL);
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bch_reg.V6.addr = 0x10;
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bch_reg.V6.power_down = 0;
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bch_reg.V6.region = 0;
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fl_reg.V6.rdn = dir;
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fl_reg.V6.dma = 1;
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fl_reg.V6.tr_count = 1;
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fl_reg.V6.async_tog_mix = 1;
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fl_reg.V6.cor_en = 1;
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fl_reg.V6.st_addr = 0;
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master_reg.d32 = nandc_readl(NANDC_MTRANS_CFG);
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master_reg.V6.bus_mode = 0;
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if (dir != 0) {
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u32 spare_sz = 64;
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for (i = 0; i < n_sec / 2; i++) {
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if (spare) {
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master.spare_buf[i * spare_sz / 4] =
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(p_spare_tmp[0]) |
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((u32)p_spare_tmp[1] << 16);
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p_spare_tmp += 2;
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} else {
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master.spare_buf[i * spare_sz / 4] =
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0xffffffff;
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}
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}
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}
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fl_reg.V6.page_num = (n_sec + 1) / 2;
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master.page_vir = (u32 *)((data == (u32 *)NULL) ?
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master.page_buf :
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(u32 *)data);
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master.spare_vir = (u32 *)master.spare_buf;
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master.page_phy = (u32)((unsigned long)master.page_vir);
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master.spare_phy = (u32)((unsigned long)master.spare_vir);
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vir_addr = ((unsigned long)master.page_phy);
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flush_dcache_range(vir_addr & (~0x3FuL),
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((vir_addr + 63) & (~0x3FuL)) +
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fl_reg.V6.page_num * 1024);
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vir_addr = ((unsigned long)master.spare_phy);
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flush_dcache_range(vir_addr & (~0x3FuL),
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((vir_addr + 63) & (~0x3FuL)) +
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fl_reg.V6.page_num * 128);
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master.mapped = 1;
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nandc_writel(master.page_phy, NANDC_MTRANS_SADDR0);
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nandc_writel(master.spare_phy, NANDC_MTRANS_SADDR1);
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master_reg.d32 = 0;
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master_reg.V6.incr_num = 16;
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master_reg.V6.burst = 7;
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master_reg.V6.hsize = 2;
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master_reg.V6.bus_mode = 1;
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master_reg.V6.ahb_wr = !dir;
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master_reg.V6.ahb_wr_st = 1;
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nandc_writel(master_reg.d32, NANDC_MTRANS_CFG);
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nandc_writel(bch_reg.d32, NANDC_BCHCTL);
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nandc_writel(fl_reg.d32, NANDC_FLCTL);
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fl_reg.V6.start = 1;
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nandc_writel(fl_reg.d32, NANDC_FLCTL);
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}
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}
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/*
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* Wait for the end of data transmission
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*/
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static void nandc_xfer_done(void)
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{
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union FL_CTL_T fl_reg;
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union MTRANS_CFG_T master_reg;
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if (g_nandc_ver == 9) {
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union MTRANS_STAT_T stat_reg;
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master_reg.d32 = nandc_readl(NANDC_V9_MTRANS_CFG);
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if (master_reg.V9.ahb_wr != 0) {
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do {
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fl_reg.d32 = nandc_readl(NANDC_V9_FLCTL);
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stat_reg.d32 = nandc_readl(NANDC_V9_MTRANS_STAT);
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usleep_range(20, 30);
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} while (stat_reg.V9.mtrans_cnt < fl_reg.V9.page_num ||
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fl_reg.V9.tr_rdy == 0);
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udelay(5);
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} else {
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do {
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fl_reg.d32 = nandc_readl(NANDC_V9_FLCTL);
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usleep_range(20, 30);
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} while (fl_reg.V9.tr_rdy == 0);
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}
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} else {
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master_reg.d32 = nandc_readl(NANDC_MTRANS_CFG);
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if (master_reg.V6.bus_mode != 0) {
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union MTRANS_STAT_T stat_reg;
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if (master_reg.V6.ahb_wr != 0) {
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do {
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fl_reg.d32 = nandc_readl(NANDC_FLCTL);
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stat_reg.d32 = nandc_readl(NANDC_MTRANS_STAT);
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usleep_range(20, 30);
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} while (stat_reg.V6.mtrans_cnt < fl_reg.V6.page_num ||
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fl_reg.V6.tr_rdy == 0);
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} else {
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do {
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fl_reg.d32 = nandc_readl(NANDC_FLCTL);
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usleep_range(20, 30);
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} while (fl_reg.V6.tr_rdy == 0);
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}
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} else {
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do {
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fl_reg.d32 = nandc_readl(NANDC_FLCTL);
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} while ((fl_reg.V6.tr_rdy == 0));
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}
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}
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}
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u32 nandc_xfer_data(u8 chip_sel, u8 dir, u8 n_sec,
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u32 *p_data, u32 *p_spare)
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{
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u32 status = NAND_STS_OK;
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u32 i;
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u32 spare[16];
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union BCH_ST_T bch_st_reg;
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if (dir == NANDC_WRITE && !p_spare) {
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p_spare = (u32 *)spare;
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memset(spare, 0xFF, sizeof(spare));
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}
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nandc_xfer_start(dir, n_sec, p_data, p_spare);
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nandc_xfer_done();
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if (dir == NANDC_READ) {
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if (g_nandc_ver == 9) {
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for (i = 0; i < n_sec / 4; i++) {
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bch_st_reg.d32 = nandc_readl(NANDC_V9_BCHST(i));
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if (n_sec > 2) {
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if (bch_st_reg.V9.fail0 || bch_st_reg.V9.fail1) {
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status = NAND_STS_ECC_ERR;
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} else {
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u32 tmp = max((u32)bch_st_reg.V9.err_bits0,
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(u32)bch_st_reg.V9.err_bits1);
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status = max(tmp, status);
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}
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} else {
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if (bch_st_reg.V9.fail0)
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status = NAND_STS_ECC_ERR;
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else
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status = bch_st_reg.V9.err_bits0;
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}
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}
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if (p_spare) {
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for (i = 0; i < n_sec / 2; i++)
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p_spare[i] = master.spare_buf[i];
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}
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} else {
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for (i = 0; i < n_sec / 4 ; i++) {
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bch_st_reg.d32 = nandc_readl(NANDC_BCHST(i));
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if (bch_st_reg.V6.fail0 || bch_st_reg.V6.fail1) {
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status = NAND_STS_ECC_ERR;
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} else {
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u32 tmp = 0;
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tmp =
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max(bch_st_reg.V6.err_bits0 |
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((u32)bch_st_reg.V6.err_bits0_5 << 5),
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bch_st_reg.V6.err_bits1 |
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((u32)bch_st_reg.V6.err_bits1_5 << 5));
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status = max(tmp, status);
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}
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}
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if (p_spare) {
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u32 spare_sz = 64;
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u32 temp_data;
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u8 *p_spare_temp = (u8 *)p_spare;
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for (i = 0; i < n_sec / 2; i++) {
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temp_data = master.spare_buf[i * spare_sz / 4];
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*p_spare_temp++ = (u8)temp_data;
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*p_spare_temp++ = (u8)(temp_data >> 8);
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*p_spare_temp++ = (u8)(temp_data >> 16);
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*p_spare_temp++ = (u8)(temp_data >> 24);
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}
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}
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nandc_writel(0, NANDC_MTRANS_CFG);
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}
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}
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return status;
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}
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void nandc_clean_irq(void)
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{
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}
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