/*
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* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
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* Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <linux/libfdt.h>
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#include <mmc.h>
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#include <reset.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <linux/iopoll.h>
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struct stm32_sdmmc2_plat {
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struct mmc_config cfg;
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struct mmc mmc;
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};
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struct stm32_sdmmc2_priv {
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fdt_addr_t base;
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struct clk clk;
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struct reset_ctl reset_ctl;
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struct gpio_desc cd_gpio;
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u32 clk_reg_msk;
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u32 pwr_reg_msk;
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};
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struct stm32_sdmmc2_ctx {
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u32 cache_start;
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u32 cache_end;
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u32 data_length;
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bool dpsm_abort;
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};
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/* SDMMC REGISTERS OFFSET */
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#define SDMMC_POWER 0x00 /* SDMMC power control */
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#define SDMMC_CLKCR 0x04 /* SDMMC clock control */
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#define SDMMC_ARG 0x08 /* SDMMC argument */
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#define SDMMC_CMD 0x0C /* SDMMC command */
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#define SDMMC_RESP1 0x14 /* SDMMC response 1 */
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#define SDMMC_RESP2 0x18 /* SDMMC response 2 */
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#define SDMMC_RESP3 0x1C /* SDMMC response 3 */
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#define SDMMC_RESP4 0x20 /* SDMMC response 4 */
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#define SDMMC_DTIMER 0x24 /* SDMMC data timer */
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#define SDMMC_DLEN 0x28 /* SDMMC data length */
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#define SDMMC_DCTRL 0x2C /* SDMMC data control */
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#define SDMMC_DCOUNT 0x30 /* SDMMC data counter */
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#define SDMMC_STA 0x34 /* SDMMC status */
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#define SDMMC_ICR 0x38 /* SDMMC interrupt clear */
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#define SDMMC_MASK 0x3C /* SDMMC mask */
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#define SDMMC_IDMACTRL 0x50 /* SDMMC DMA control */
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#define SDMMC_IDMABASE0 0x58 /* SDMMC DMA buffer 0 base address */
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/* SDMMC_POWER register */
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#define SDMMC_POWER_PWRCTRL GENMASK(1, 0)
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#define SDMMC_POWER_VSWITCH BIT(2)
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#define SDMMC_POWER_VSWITCHEN BIT(3)
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#define SDMMC_POWER_DIRPOL BIT(4)
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/* SDMMC_CLKCR register */
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#define SDMMC_CLKCR_CLKDIV GENMASK(9, 0)
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#define SDMMC_CLKCR_CLKDIV_MAX SDMMC_CLKCR_CLKDIV
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#define SDMMC_CLKCR_PWRSAV BIT(12)
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#define SDMMC_CLKCR_WIDBUS_4 BIT(14)
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#define SDMMC_CLKCR_WIDBUS_8 BIT(15)
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#define SDMMC_CLKCR_NEGEDGE BIT(16)
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#define SDMMC_CLKCR_HWFC_EN BIT(17)
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#define SDMMC_CLKCR_DDR BIT(18)
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#define SDMMC_CLKCR_BUSSPEED BIT(19)
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#define SDMMC_CLKCR_SELCLKRX GENMASK(21, 20)
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/* SDMMC_CMD register */
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#define SDMMC_CMD_CMDINDEX GENMASK(5, 0)
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#define SDMMC_CMD_CMDTRANS BIT(6)
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#define SDMMC_CMD_CMDSTOP BIT(7)
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#define SDMMC_CMD_WAITRESP GENMASK(9, 8)
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#define SDMMC_CMD_WAITRESP_0 BIT(8)
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#define SDMMC_CMD_WAITRESP_1 BIT(9)
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#define SDMMC_CMD_WAITINT BIT(10)
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#define SDMMC_CMD_WAITPEND BIT(11)
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#define SDMMC_CMD_CPSMEN BIT(12)
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#define SDMMC_CMD_DTHOLD BIT(13)
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#define SDMMC_CMD_BOOTMODE BIT(14)
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#define SDMMC_CMD_BOOTEN BIT(15)
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#define SDMMC_CMD_CMDSUSPEND BIT(16)
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/* SDMMC_DCTRL register */
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#define SDMMC_DCTRL_DTEN BIT(0)
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#define SDMMC_DCTRL_DTDIR BIT(1)
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#define SDMMC_DCTRL_DTMODE GENMASK(3, 2)
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#define SDMMC_DCTRL_DBLOCKSIZE GENMASK(7, 4)
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#define SDMMC_DCTRL_DBLOCKSIZE_SHIFT 4
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#define SDMMC_DCTRL_RWSTART BIT(8)
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#define SDMMC_DCTRL_RWSTOP BIT(9)
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#define SDMMC_DCTRL_RWMOD BIT(10)
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#define SDMMC_DCTRL_SDMMCEN BIT(11)
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#define SDMMC_DCTRL_BOOTACKEN BIT(12)
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#define SDMMC_DCTRL_FIFORST BIT(13)
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/* SDMMC_STA register */
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#define SDMMC_STA_CCRCFAIL BIT(0)
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#define SDMMC_STA_DCRCFAIL BIT(1)
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#define SDMMC_STA_CTIMEOUT BIT(2)
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#define SDMMC_STA_DTIMEOUT BIT(3)
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#define SDMMC_STA_TXUNDERR BIT(4)
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#define SDMMC_STA_RXOVERR BIT(5)
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#define SDMMC_STA_CMDREND BIT(6)
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#define SDMMC_STA_CMDSENT BIT(7)
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#define SDMMC_STA_DATAEND BIT(8)
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#define SDMMC_STA_DHOLD BIT(9)
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#define SDMMC_STA_DBCKEND BIT(10)
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#define SDMMC_STA_DABORT BIT(11)
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#define SDMMC_STA_DPSMACT BIT(12)
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#define SDMMC_STA_CPSMACT BIT(13)
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#define SDMMC_STA_TXFIFOHE BIT(14)
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#define SDMMC_STA_RXFIFOHF BIT(15)
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#define SDMMC_STA_TXFIFOF BIT(16)
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#define SDMMC_STA_RXFIFOF BIT(17)
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#define SDMMC_STA_TXFIFOE BIT(18)
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#define SDMMC_STA_RXFIFOE BIT(19)
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#define SDMMC_STA_BUSYD0 BIT(20)
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#define SDMMC_STA_BUSYD0END BIT(21)
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#define SDMMC_STA_SDMMCIT BIT(22)
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#define SDMMC_STA_ACKFAIL BIT(23)
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#define SDMMC_STA_ACKTIMEOUT BIT(24)
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#define SDMMC_STA_VSWEND BIT(25)
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#define SDMMC_STA_CKSTOP BIT(26)
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#define SDMMC_STA_IDMATE BIT(27)
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#define SDMMC_STA_IDMABTC BIT(28)
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/* SDMMC_ICR register */
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#define SDMMC_ICR_CCRCFAILC BIT(0)
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#define SDMMC_ICR_DCRCFAILC BIT(1)
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#define SDMMC_ICR_CTIMEOUTC BIT(2)
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#define SDMMC_ICR_DTIMEOUTC BIT(3)
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#define SDMMC_ICR_TXUNDERRC BIT(4)
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#define SDMMC_ICR_RXOVERRC BIT(5)
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#define SDMMC_ICR_CMDRENDC BIT(6)
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#define SDMMC_ICR_CMDSENTC BIT(7)
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#define SDMMC_ICR_DATAENDC BIT(8)
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#define SDMMC_ICR_DHOLDC BIT(9)
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#define SDMMC_ICR_DBCKENDC BIT(10)
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#define SDMMC_ICR_DABORTC BIT(11)
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#define SDMMC_ICR_BUSYD0ENDC BIT(21)
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#define SDMMC_ICR_SDMMCITC BIT(22)
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#define SDMMC_ICR_ACKFAILC BIT(23)
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#define SDMMC_ICR_ACKTIMEOUTC BIT(24)
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#define SDMMC_ICR_VSWENDC BIT(25)
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#define SDMMC_ICR_CKSTOPC BIT(26)
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#define SDMMC_ICR_IDMATEC BIT(27)
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#define SDMMC_ICR_IDMABTCC BIT(28)
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#define SDMMC_ICR_STATIC_FLAGS ((GENMASK(28, 21)) | (GENMASK(11, 0)))
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/* SDMMC_MASK register */
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#define SDMMC_MASK_CCRCFAILIE BIT(0)
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#define SDMMC_MASK_DCRCFAILIE BIT(1)
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#define SDMMC_MASK_CTIMEOUTIE BIT(2)
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#define SDMMC_MASK_DTIMEOUTIE BIT(3)
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#define SDMMC_MASK_TXUNDERRIE BIT(4)
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#define SDMMC_MASK_RXOVERRIE BIT(5)
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#define SDMMC_MASK_CMDRENDIE BIT(6)
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#define SDMMC_MASK_CMDSENTIE BIT(7)
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#define SDMMC_MASK_DATAENDIE BIT(8)
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#define SDMMC_MASK_DHOLDIE BIT(9)
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#define SDMMC_MASK_DBCKENDIE BIT(10)
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#define SDMMC_MASK_DABORTIE BIT(11)
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#define SDMMC_MASK_TXFIFOHEIE BIT(14)
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#define SDMMC_MASK_RXFIFOHFIE BIT(15)
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#define SDMMC_MASK_RXFIFOFIE BIT(17)
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#define SDMMC_MASK_TXFIFOEIE BIT(18)
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#define SDMMC_MASK_BUSYD0ENDIE BIT(21)
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#define SDMMC_MASK_SDMMCITIE BIT(22)
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#define SDMMC_MASK_ACKFAILIE BIT(23)
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#define SDMMC_MASK_ACKTIMEOUTIE BIT(24)
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#define SDMMC_MASK_VSWENDIE BIT(25)
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#define SDMMC_MASK_CKSTOPIE BIT(26)
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#define SDMMC_MASK_IDMABTCIE BIT(28)
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/* SDMMC_IDMACTRL register */
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#define SDMMC_IDMACTRL_IDMAEN BIT(0)
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#define SDMMC_CMD_TIMEOUT 0xFFFFFFFF
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DECLARE_GLOBAL_DATA_PTR;
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static void stm32_sdmmc2_start_data(struct stm32_sdmmc2_priv *priv,
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struct mmc_data *data,
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struct stm32_sdmmc2_ctx *ctx)
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{
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u32 data_ctrl, idmabase0;
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/* Configure the SDMMC DPSM (Data Path State Machine) */
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data_ctrl = (__ilog2(data->blocksize) <<
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SDMMC_DCTRL_DBLOCKSIZE_SHIFT) &
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SDMMC_DCTRL_DBLOCKSIZE;
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if (data->flags & MMC_DATA_READ) {
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data_ctrl |= SDMMC_DCTRL_DTDIR;
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idmabase0 = (u32)data->dest;
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} else {
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idmabase0 = (u32)data->src;
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}
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/* Set the SDMMC Data TimeOut value */
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writel(SDMMC_CMD_TIMEOUT, priv->base + SDMMC_DTIMER);
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/* Set the SDMMC DataLength value */
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writel(ctx->data_length, priv->base + SDMMC_DLEN);
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/* Write to SDMMC DCTRL */
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writel(data_ctrl, priv->base + SDMMC_DCTRL);
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/* Cache align */
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ctx->cache_start = rounddown(idmabase0, ARCH_DMA_MINALIGN);
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ctx->cache_end = roundup(idmabase0 + ctx->data_length,
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ARCH_DMA_MINALIGN);
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/*
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* Flush data cache before DMA start (clean and invalidate)
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* Clean also needed for read
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* Avoid issue on buffer not cached-aligned
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*/
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flush_dcache_range(ctx->cache_start, ctx->cache_end);
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/* Enable internal DMA */
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writel(idmabase0, priv->base + SDMMC_IDMABASE0);
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writel(SDMMC_IDMACTRL_IDMAEN, priv->base + SDMMC_IDMACTRL);
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}
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static void stm32_sdmmc2_start_cmd(struct stm32_sdmmc2_priv *priv,
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struct mmc_cmd *cmd, u32 cmd_param)
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{
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if (readl(priv->base + SDMMC_ARG) & SDMMC_CMD_CPSMEN)
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writel(0, priv->base + SDMMC_ARG);
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cmd_param |= cmd->cmdidx | SDMMC_CMD_CPSMEN;
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if (cmd->resp_type & MMC_RSP_PRESENT) {
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if (cmd->resp_type & MMC_RSP_136)
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cmd_param |= SDMMC_CMD_WAITRESP;
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else if (cmd->resp_type & MMC_RSP_CRC)
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cmd_param |= SDMMC_CMD_WAITRESP_0;
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else
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cmd_param |= SDMMC_CMD_WAITRESP_1;
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}
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/* Clear flags */
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writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
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/* Set SDMMC argument value */
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writel(cmd->cmdarg, priv->base + SDMMC_ARG);
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/* Set SDMMC command parameters */
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writel(cmd_param, priv->base + SDMMC_CMD);
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}
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static int stm32_sdmmc2_end_cmd(struct stm32_sdmmc2_priv *priv,
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struct mmc_cmd *cmd,
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struct stm32_sdmmc2_ctx *ctx)
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{
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u32 mask = SDMMC_STA_CTIMEOUT;
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u32 status;
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int ret;
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if (cmd->resp_type & MMC_RSP_PRESENT) {
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mask |= SDMMC_STA_CMDREND;
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if (cmd->resp_type & MMC_RSP_CRC)
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mask |= SDMMC_STA_CCRCFAIL;
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} else {
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mask |= SDMMC_STA_CMDSENT;
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}
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/* Polling status register */
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ret = readl_poll_timeout(priv->base + SDMMC_STA, status, status & mask,
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10000);
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if (ret < 0) {
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debug("%s: timeout reading SDMMC_STA register\n", __func__);
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ctx->dpsm_abort = true;
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return ret;
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}
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/* Check status */
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if (status & SDMMC_STA_CTIMEOUT) {
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debug("%s: error SDMMC_STA_CTIMEOUT (0x%x) for cmd %d\n",
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__func__, status, cmd->cmdidx);
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ctx->dpsm_abort = true;
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return -ETIMEDOUT;
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}
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if (status & SDMMC_STA_CCRCFAIL && cmd->resp_type & MMC_RSP_CRC) {
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debug("%s: error SDMMC_STA_CCRCFAIL (0x%x) for cmd %d\n",
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__func__, status, cmd->cmdidx);
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ctx->dpsm_abort = true;
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return -EILSEQ;
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}
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if (status & SDMMC_STA_CMDREND && cmd->resp_type & MMC_RSP_PRESENT) {
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cmd->response[0] = readl(priv->base + SDMMC_RESP1);
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if (cmd->resp_type & MMC_RSP_136) {
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cmd->response[1] = readl(priv->base + SDMMC_RESP2);
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cmd->response[2] = readl(priv->base + SDMMC_RESP3);
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cmd->response[3] = readl(priv->base + SDMMC_RESP4);
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}
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}
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return 0;
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}
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static int stm32_sdmmc2_end_data(struct stm32_sdmmc2_priv *priv,
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struct mmc_cmd *cmd,
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struct mmc_data *data,
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struct stm32_sdmmc2_ctx *ctx)
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{
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u32 mask = SDMMC_STA_DCRCFAIL | SDMMC_STA_DTIMEOUT |
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SDMMC_STA_IDMATE | SDMMC_STA_DATAEND;
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u32 status;
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if (data->flags & MMC_DATA_READ)
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mask |= SDMMC_STA_RXOVERR;
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else
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mask |= SDMMC_STA_TXUNDERR;
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status = readl(priv->base + SDMMC_STA);
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while (!(status & mask))
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status = readl(priv->base + SDMMC_STA);
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/*
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* Need invalidate the dcache again to avoid any
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* cache-refill during the DMA operations (pre-fetching)
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*/
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if (data->flags & MMC_DATA_READ)
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invalidate_dcache_range(ctx->cache_start, ctx->cache_end);
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if (status & SDMMC_STA_DCRCFAIL) {
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debug("%s: error SDMMC_STA_DCRCFAIL (0x%x) for cmd %d\n",
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__func__, status, cmd->cmdidx);
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if (readl(priv->base + SDMMC_DCOUNT))
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ctx->dpsm_abort = true;
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return -EILSEQ;
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}
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if (status & SDMMC_STA_DTIMEOUT) {
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debug("%s: error SDMMC_STA_DTIMEOUT (0x%x) for cmd %d\n",
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__func__, status, cmd->cmdidx);
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ctx->dpsm_abort = true;
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return -ETIMEDOUT;
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}
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if (status & SDMMC_STA_TXUNDERR) {
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debug("%s: error SDMMC_STA_TXUNDERR (0x%x) for cmd %d\n",
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__func__, status, cmd->cmdidx);
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ctx->dpsm_abort = true;
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return -EIO;
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}
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if (status & SDMMC_STA_RXOVERR) {
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debug("%s: error SDMMC_STA_RXOVERR (0x%x) for cmd %d\n",
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__func__, status, cmd->cmdidx);
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ctx->dpsm_abort = true;
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return -EIO;
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}
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if (status & SDMMC_STA_IDMATE) {
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debug("%s: error SDMMC_STA_IDMATE (0x%x) for cmd %d\n",
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__func__, status, cmd->cmdidx);
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ctx->dpsm_abort = true;
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return -EIO;
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}
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return 0;
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}
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static int stm32_sdmmc2_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
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struct mmc_data *data)
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{
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struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
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struct stm32_sdmmc2_ctx ctx;
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u32 cmdat = data ? SDMMC_CMD_CMDTRANS : 0;
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int ret, retry = 3;
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retry_cmd:
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ctx.data_length = 0;
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ctx.dpsm_abort = false;
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if (data) {
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ctx.data_length = data->blocks * data->blocksize;
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stm32_sdmmc2_start_data(priv, data, &ctx);
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}
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stm32_sdmmc2_start_cmd(priv, cmd, cmdat);
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debug("%s: send cmd %d data: 0x%x @ 0x%x\n",
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__func__, cmd->cmdidx,
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data ? ctx.data_length : 0, (unsigned int)data);
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ret = stm32_sdmmc2_end_cmd(priv, cmd, &ctx);
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if (data && !ret)
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ret = stm32_sdmmc2_end_data(priv, cmd, data, &ctx);
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/* Clear flags */
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writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
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if (data)
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writel(0x0, priv->base + SDMMC_IDMACTRL);
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/*
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* To stop Data Path State Machine, a stop_transmission command
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* shall be send on cmd or data errors.
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*/
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if (ctx.dpsm_abort && (cmd->cmdidx != MMC_CMD_STOP_TRANSMISSION)) {
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struct mmc_cmd stop_cmd;
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stop_cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
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stop_cmd.cmdarg = 0;
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stop_cmd.resp_type = MMC_RSP_R1b;
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debug("%s: send STOP command to abort dpsm treatments\n",
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__func__);
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stm32_sdmmc2_start_cmd(priv, &stop_cmd, SDMMC_CMD_CMDSTOP);
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stm32_sdmmc2_end_cmd(priv, &stop_cmd, &ctx);
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writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
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}
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if ((ret != -ETIMEDOUT) && (ret != 0) && retry) {
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printf("%s: cmd %d failed, retrying ...\n",
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__func__, cmd->cmdidx);
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retry--;
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goto retry_cmd;
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}
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debug("%s: end for CMD %d, ret = %d\n", __func__, cmd->cmdidx, ret);
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return ret;
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}
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static void stm32_sdmmc2_pwron(struct stm32_sdmmc2_priv *priv)
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{
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/* Reset */
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reset_assert(&priv->reset_ctl);
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udelay(2);
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reset_deassert(&priv->reset_ctl);
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udelay(1000);
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/* Set Power State to ON */
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writel(SDMMC_POWER_PWRCTRL | priv->pwr_reg_msk, priv->base + SDMMC_POWER);
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/*
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* 1ms: required power up waiting time before starting the
|
* SD initialization sequence
|
*/
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udelay(1000);
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}
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#define IS_RISING_EDGE(reg) (reg & SDMMC_CLKCR_NEGEDGE ? 0 : 1)
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static int stm32_sdmmc2_set_ios(struct udevice *dev)
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{
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struct mmc *mmc = mmc_get_mmc_dev(dev);
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struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
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struct stm32_sdmmc2_plat *plat = dev_get_platdata(dev);
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struct mmc_config *cfg = &plat->cfg;
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u32 desired = mmc->clock;
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u32 sys_clock = clk_get_rate(&priv->clk);
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u32 clk = 0;
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|
debug("%s: bus_with = %d, clock = %d\n", __func__,
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mmc->bus_width, mmc->clock);
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if ((mmc->bus_width == 1) && (desired == cfg->f_min))
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stm32_sdmmc2_pwron(priv);
|
|
/*
|
* clk_div = 0 => command and data generated on SDMMCCLK falling edge
|
* clk_div > 0 and NEGEDGE = 0 => command and data generated on
|
* SDMMCCLK rising edge
|
* clk_div > 0 and NEGEDGE = 1 => command and data generated on
|
* SDMMCCLK falling edge
|
*/
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if (desired && ((sys_clock > desired) ||
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IS_RISING_EDGE(priv->clk_reg_msk))) {
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clk = DIV_ROUND_UP(sys_clock, 2 * desired);
|
if (clk > SDMMC_CLKCR_CLKDIV_MAX)
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clk = SDMMC_CLKCR_CLKDIV_MAX;
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}
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if (mmc->bus_width == 4)
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clk |= SDMMC_CLKCR_WIDBUS_4;
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if (mmc->bus_width == 8)
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clk |= SDMMC_CLKCR_WIDBUS_8;
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writel(clk | priv->clk_reg_msk, priv->base + SDMMC_CLKCR);
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return 0;
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}
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static int stm32_sdmmc2_getcd(struct udevice *dev)
|
{
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struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
|
|
debug("stm32_sdmmc2_getcd called\n");
|
|
if (dm_gpio_is_valid(&priv->cd_gpio))
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return dm_gpio_get_value(&priv->cd_gpio);
|
|
return 1;
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}
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static const struct dm_mmc_ops stm32_sdmmc2_ops = {
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.send_cmd = stm32_sdmmc2_send_cmd,
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.set_ios = stm32_sdmmc2_set_ios,
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.get_cd = stm32_sdmmc2_getcd,
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};
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static int stm32_sdmmc2_probe(struct udevice *dev)
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{
|
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
|
struct stm32_sdmmc2_plat *plat = dev_get_platdata(dev);
|
struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
|
struct mmc_config *cfg = &plat->cfg;
|
int ret;
|
|
priv->base = dev_read_addr(dev);
|
if (priv->base == FDT_ADDR_T_NONE)
|
return -EINVAL;
|
|
if (dev_read_bool(dev, "st,negedge"))
|
priv->clk_reg_msk |= SDMMC_CLKCR_NEGEDGE;
|
if (dev_read_bool(dev, "st,dirpol"))
|
priv->pwr_reg_msk |= SDMMC_POWER_DIRPOL;
|
|
ret = clk_get_by_index(dev, 0, &priv->clk);
|
if (ret)
|
return ret;
|
|
ret = clk_enable(&priv->clk);
|
if (ret)
|
goto clk_free;
|
|
ret = reset_get_by_index(dev, 0, &priv->reset_ctl);
|
if (ret)
|
goto clk_disable;
|
|
gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
|
GPIOD_IS_IN);
|
|
cfg->f_min = 400000;
|
cfg->f_max = dev_read_u32_default(dev, "max-frequency", 52000000);
|
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
|
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
|
cfg->name = "STM32 SDMMC2";
|
|
cfg->host_caps = 0;
|
if (cfg->f_max > 25000000)
|
cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
|
|
switch (dev_read_u32_default(dev, "bus-width", 1)) {
|
case 8:
|
cfg->host_caps |= MMC_MODE_8BIT;
|
case 4:
|
cfg->host_caps |= MMC_MODE_4BIT;
|
break;
|
case 1:
|
break;
|
default:
|
pr_err("invalid \"bus-width\" property, force to 1\n");
|
}
|
|
upriv->mmc = &plat->mmc;
|
|
return 0;
|
|
clk_disable:
|
clk_disable(&priv->clk);
|
clk_free:
|
clk_free(&priv->clk);
|
|
return ret;
|
}
|
|
int stm32_sdmmc_bind(struct udevice *dev)
|
{
|
struct stm32_sdmmc2_plat *plat = dev_get_platdata(dev);
|
|
return mmc_bind(dev, &plat->mmc, &plat->cfg);
|
}
|
|
static const struct udevice_id stm32_sdmmc2_ids[] = {
|
{ .compatible = "st,stm32-sdmmc2" },
|
{ }
|
};
|
|
U_BOOT_DRIVER(stm32_sdmmc2) = {
|
.name = "stm32_sdmmc2",
|
.id = UCLASS_MMC,
|
.of_match = stm32_sdmmc2_ids,
|
.ops = &stm32_sdmmc2_ops,
|
.probe = stm32_sdmmc2_probe,
|
.bind = stm32_sdmmc_bind,
|
.priv_auto_alloc_size = sizeof(struct stm32_sdmmc2_priv),
|
.platdata_auto_alloc_size = sizeof(struct stm32_sdmmc2_plat),
|
};
|
