/*
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* Copyright (c) 2017
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* Patrice Chotard <patrice.chotard@st.com>
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <dm.h>
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#include <mmc.h>
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#include <sdhci.h>
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#include <asm/arch/sdhci.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct sti_sdhci_plat {
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struct mmc_config cfg;
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struct mmc mmc;
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};
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/*
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* used to get access to MMC1 reset,
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* will be removed when STi reset driver will be available
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*/
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#define STIH410_SYSCONF5_BASE 0x092b0000
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/**
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* sti_mmc_core_config: configure the Arasan HC
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* @regbase: base address
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* @mmc_instance: mmc instance id
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* Description: this function is to configure the Arasan MMC HC.
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* This should be called when the system starts in case of, on the SoC,
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* it is needed to configure the host controller.
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* This happens on some SoCs, i.e. StiH410, where the MMC0 inside the flashSS
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* needs to be configured as MMC 4.5 to have full capabilities.
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* W/o these settings the SDHCI could configure and use the embedded controller
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* with limited features.
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*/
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static void sti_mmc_core_config(const u32 regbase, int mmc_instance)
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{
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unsigned long *sysconf;
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/* only MMC1 has a reset line */
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if (mmc_instance) {
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sysconf = (unsigned long *)(STIH410_SYSCONF5_BASE +
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ST_MMC_CCONFIG_REG_5);
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generic_set_bit(SYSCONF_MMC1_ENABLE_BIT, sysconf);
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}
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writel(STI_FLASHSS_MMC_CORE_CONFIG_1,
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regbase + FLASHSS_MMC_CORE_CONFIG_1);
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if (mmc_instance) {
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writel(STI_FLASHSS_MMC_CORE_CONFIG2,
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regbase + FLASHSS_MMC_CORE_CONFIG_2);
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writel(STI_FLASHSS_MMC_CORE_CONFIG3,
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regbase + FLASHSS_MMC_CORE_CONFIG_3);
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} else {
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writel(STI_FLASHSS_SDCARD_CORE_CONFIG2,
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regbase + FLASHSS_MMC_CORE_CONFIG_2);
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writel(STI_FLASHSS_SDCARD_CORE_CONFIG3,
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regbase + FLASHSS_MMC_CORE_CONFIG_3);
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}
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writel(STI_FLASHSS_MMC_CORE_CONFIG4,
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regbase + FLASHSS_MMC_CORE_CONFIG_4);
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}
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static int sti_sdhci_probe(struct udevice *dev)
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{
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struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
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struct sti_sdhci_plat *plat = dev_get_platdata(dev);
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struct sdhci_host *host = dev_get_priv(dev);
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int ret, mmc_instance;
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/*
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* identify current mmc instance, mmc1 has a reset, not mmc0
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* MMC0 is wired to the SD slot,
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* MMC1 is wired on the high speed connector
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*/
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if (fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "resets", NULL))
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mmc_instance = 1;
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else
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mmc_instance = 0;
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sti_mmc_core_config((const u32) host->ioaddr, mmc_instance);
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host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
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SDHCI_QUIRK_32BIT_DMA_ADDR |
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SDHCI_QUIRK_NO_HISPD_BIT;
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host->host_caps = MMC_MODE_DDR_52MHz;
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ret = sdhci_setup_cfg(&plat->cfg, host, 50000000, 400000);
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if (ret)
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return ret;
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host->mmc = &plat->mmc;
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host->mmc->priv = host;
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host->mmc->dev = dev;
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upriv->mmc = host->mmc;
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return sdhci_probe(dev);
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}
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static int sti_sdhci_ofdata_to_platdata(struct udevice *dev)
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{
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struct sdhci_host *host = dev_get_priv(dev);
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host->name = strdup(dev->name);
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host->ioaddr = (void *)devfdt_get_addr(dev);
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host->bus_width = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
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"bus-width", 4);
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return 0;
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}
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static int sti_sdhci_bind(struct udevice *dev)
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{
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struct sti_sdhci_plat *plat = dev_get_platdata(dev);
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return sdhci_bind(dev, &plat->mmc, &plat->cfg);
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}
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static const struct udevice_id sti_sdhci_ids[] = {
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{ .compatible = "st,sdhci" },
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{ }
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};
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U_BOOT_DRIVER(sti_mmc) = {
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.name = "sti_sdhci",
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.id = UCLASS_MMC,
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.of_match = sti_sdhci_ids,
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.bind = sti_sdhci_bind,
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.ops = &sdhci_ops,
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.ofdata_to_platdata = sti_sdhci_ofdata_to_platdata,
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.probe = sti_sdhci_probe,
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.priv_auto_alloc_size = sizeof(struct sdhci_host),
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.platdata_auto_alloc_size = sizeof(struct sti_sdhci_plat),
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};
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