/*
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* (C) Copyright 2013 Altera Corporation <www.altera.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/clock_manager.h>
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#include <asm/arch/system_manager.h>
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#include <dm.h>
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#include <dwmmc.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <linux/libfdt.h>
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#include <linux/err.h>
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#include <malloc.h>
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DECLARE_GLOBAL_DATA_PTR;
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static const struct socfpga_clock_manager *clock_manager_base =
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(void *)SOCFPGA_CLKMGR_ADDRESS;
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static const struct socfpga_system_manager *system_manager_base =
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(void *)SOCFPGA_SYSMGR_ADDRESS;
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struct socfpga_dwmci_plat {
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struct mmc_config cfg;
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struct mmc mmc;
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};
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/* socfpga implmentation specific driver private data */
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struct dwmci_socfpga_priv_data {
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struct dwmci_host host;
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unsigned int drvsel;
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unsigned int smplsel;
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};
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static void socfpga_dwmci_clksel(struct dwmci_host *host)
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{
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struct dwmci_socfpga_priv_data *priv = host->priv;
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u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) |
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((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT);
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/* Disable SDMMC clock. */
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clrbits_le32(&clock_manager_base->per_pll.en,
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CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
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debug("%s: drvsel %d smplsel %d\n", __func__,
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priv->drvsel, priv->smplsel);
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writel(sdmmc_mask, &system_manager_base->sdmmcgrp_ctrl);
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debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
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readl(&system_manager_base->sdmmcgrp_ctrl));
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/* Enable SDMMC clock */
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setbits_le32(&clock_manager_base->per_pll.en,
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CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
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}
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static int socfpga_dwmmc_ofdata_to_platdata(struct udevice *dev)
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{
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/* FIXME: probe from DT eventually too/ */
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const unsigned long clk = cm_get_mmc_controller_clk_hz();
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struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
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struct dwmci_host *host = &priv->host;
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int fifo_depth;
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if (clk == 0) {
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printf("DWMMC: MMC clock is zero!");
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return -EINVAL;
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}
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fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
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"fifo-depth", 0);
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if (fifo_depth < 0) {
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printf("DWMMC: Can't get FIFO depth\n");
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return -EINVAL;
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}
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host->name = dev->name;
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host->ioaddr = (void *)devfdt_get_addr(dev);
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host->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
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"bus-width", 4);
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host->clksel = socfpga_dwmci_clksel;
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/*
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* TODO(sjg@chromium.org): Remove the need for this hack.
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* We only have one dwmmc block on gen5 SoCFPGA.
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*/
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host->dev_index = 0;
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/* Fixed clock divide by 4 which due to the SDMMC wrapper */
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host->bus_hz = clk;
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host->fifoth_val = MSIZE(0x2) |
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RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2);
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priv->drvsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
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"drvsel", 3);
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priv->smplsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
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"smplsel", 0);
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host->priv = priv;
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return 0;
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}
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static int socfpga_dwmmc_probe(struct udevice *dev)
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{
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#ifdef CONFIG_BLK
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struct socfpga_dwmci_plat *plat = dev_get_platdata(dev);
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#endif
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struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
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struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
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struct dwmci_host *host = &priv->host;
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#ifdef CONFIG_BLK
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dwmci_setup_cfg(&plat->cfg, host, host->bus_hz, 400000);
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host->mmc = &plat->mmc;
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#else
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int ret;
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ret = add_dwmci(host, host->bus_hz, 400000);
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if (ret)
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return ret;
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#endif
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host->mmc->priv = &priv->host;
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upriv->mmc = host->mmc;
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host->mmc->dev = dev;
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return 0;
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}
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static int socfpga_dwmmc_bind(struct udevice *dev)
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{
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#ifdef CONFIG_BLK
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struct socfpga_dwmci_plat *plat = dev_get_platdata(dev);
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int ret;
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ret = dwmci_bind(dev, &plat->mmc, &plat->cfg);
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if (ret)
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return ret;
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#endif
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return 0;
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}
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static const struct udevice_id socfpga_dwmmc_ids[] = {
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{ .compatible = "altr,socfpga-dw-mshc" },
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{ }
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};
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U_BOOT_DRIVER(socfpga_dwmmc_drv) = {
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.name = "socfpga_dwmmc",
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.id = UCLASS_MMC,
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.of_match = socfpga_dwmmc_ids,
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.ofdata_to_platdata = socfpga_dwmmc_ofdata_to_platdata,
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.ops = &dm_dwmci_ops,
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.bind = socfpga_dwmmc_bind,
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.probe = socfpga_dwmmc_probe,
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.priv_auto_alloc_size = sizeof(struct dwmci_socfpga_priv_data),
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.platdata_auto_alloc_size = sizeof(struct socfpga_dwmci_plat),
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};
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