/*
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* drivers/mmc/sh_sdhi.c
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*
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* SD/MMC driver for Renesas rmobile ARM SoCs.
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*
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* Copyright (C) 2011,2013-2017 Renesas Electronics Corporation
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* Copyright (C) 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
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* Copyright (C) 2008-2009 Renesas Solutions Corp.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <malloc.h>
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#include <mmc.h>
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#include <dm.h>
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#include <linux/errno.h>
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#include <linux/compat.h>
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#include <linux/io.h>
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#include <linux/sizes.h>
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#include <asm/arch/rmobile.h>
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#include <asm/arch/sh_sdhi.h>
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#include <clk.h>
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#define DRIVER_NAME "sh-sdhi"
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struct sh_sdhi_host {
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void __iomem *addr;
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int ch;
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int bus_shift;
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unsigned long quirks;
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unsigned char wait_int;
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unsigned char sd_error;
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unsigned char detect_waiting;
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unsigned char app_cmd;
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};
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static inline void sh_sdhi_writeq(struct sh_sdhi_host *host, int reg, u64 val)
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{
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writeq(val, host->addr + (reg << host->bus_shift));
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}
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static inline u64 sh_sdhi_readq(struct sh_sdhi_host *host, int reg)
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{
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return readq(host->addr + (reg << host->bus_shift));
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}
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static inline void sh_sdhi_writew(struct sh_sdhi_host *host, int reg, u16 val)
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{
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writew(val, host->addr + (reg << host->bus_shift));
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}
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static inline u16 sh_sdhi_readw(struct sh_sdhi_host *host, int reg)
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{
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return readw(host->addr + (reg << host->bus_shift));
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}
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static void sh_sdhi_detect(struct sh_sdhi_host *host)
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{
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sh_sdhi_writew(host, SDHI_OPTION,
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OPT_BUS_WIDTH_1 | sh_sdhi_readw(host, SDHI_OPTION));
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host->detect_waiting = 0;
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}
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static int sh_sdhi_intr(void *dev_id)
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{
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struct sh_sdhi_host *host = dev_id;
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int state1 = 0, state2 = 0;
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state1 = sh_sdhi_readw(host, SDHI_INFO1);
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state2 = sh_sdhi_readw(host, SDHI_INFO2);
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debug("%s: state1 = %x, state2 = %x\n", __func__, state1, state2);
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/* CARD Insert */
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if (state1 & INFO1_CARD_IN) {
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sh_sdhi_writew(host, SDHI_INFO1, ~INFO1_CARD_IN);
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if (!host->detect_waiting) {
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host->detect_waiting = 1;
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sh_sdhi_detect(host);
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}
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sh_sdhi_writew(host, SDHI_INFO1_MASK, INFO1M_RESP_END |
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INFO1M_ACCESS_END | INFO1M_CARD_IN |
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INFO1M_DATA3_CARD_RE | INFO1M_DATA3_CARD_IN);
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return -EAGAIN;
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}
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/* CARD Removal */
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if (state1 & INFO1_CARD_RE) {
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sh_sdhi_writew(host, SDHI_INFO1, ~INFO1_CARD_RE);
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if (!host->detect_waiting) {
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host->detect_waiting = 1;
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sh_sdhi_detect(host);
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}
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sh_sdhi_writew(host, SDHI_INFO1_MASK, INFO1M_RESP_END |
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INFO1M_ACCESS_END | INFO1M_CARD_RE |
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INFO1M_DATA3_CARD_RE | INFO1M_DATA3_CARD_IN);
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sh_sdhi_writew(host, SDHI_SDIO_INFO1_MASK, SDIO_INFO1M_ON);
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sh_sdhi_writew(host, SDHI_SDIO_MODE, SDIO_MODE_OFF);
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return -EAGAIN;
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}
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if (state2 & INFO2_ALL_ERR) {
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sh_sdhi_writew(host, SDHI_INFO2,
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(unsigned short)~(INFO2_ALL_ERR));
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sh_sdhi_writew(host, SDHI_INFO2_MASK,
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INFO2M_ALL_ERR |
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sh_sdhi_readw(host, SDHI_INFO2_MASK));
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host->sd_error = 1;
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host->wait_int = 1;
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return 0;
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}
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/* Respons End */
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if (state1 & INFO1_RESP_END) {
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sh_sdhi_writew(host, SDHI_INFO1, ~INFO1_RESP_END);
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sh_sdhi_writew(host, SDHI_INFO1_MASK,
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INFO1M_RESP_END |
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sh_sdhi_readw(host, SDHI_INFO1_MASK));
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host->wait_int = 1;
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return 0;
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}
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/* SD_BUF Read Enable */
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if (state2 & INFO2_BRE_ENABLE) {
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sh_sdhi_writew(host, SDHI_INFO2, ~INFO2_BRE_ENABLE);
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sh_sdhi_writew(host, SDHI_INFO2_MASK,
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INFO2M_BRE_ENABLE | INFO2M_BUF_ILL_READ |
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sh_sdhi_readw(host, SDHI_INFO2_MASK));
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host->wait_int = 1;
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return 0;
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}
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/* SD_BUF Write Enable */
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if (state2 & INFO2_BWE_ENABLE) {
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sh_sdhi_writew(host, SDHI_INFO2, ~INFO2_BWE_ENABLE);
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sh_sdhi_writew(host, SDHI_INFO2_MASK,
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INFO2_BWE_ENABLE | INFO2M_BUF_ILL_WRITE |
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sh_sdhi_readw(host, SDHI_INFO2_MASK));
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host->wait_int = 1;
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return 0;
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}
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/* Access End */
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if (state1 & INFO1_ACCESS_END) {
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sh_sdhi_writew(host, SDHI_INFO1, ~INFO1_ACCESS_END);
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sh_sdhi_writew(host, SDHI_INFO1_MASK,
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INFO1_ACCESS_END |
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sh_sdhi_readw(host, SDHI_INFO1_MASK));
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host->wait_int = 1;
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return 0;
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}
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return -EAGAIN;
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}
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static int sh_sdhi_wait_interrupt_flag(struct sh_sdhi_host *host)
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{
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int timeout = 10000000;
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while (1) {
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timeout--;
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if (timeout < 0) {
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debug(DRIVER_NAME": %s timeout\n", __func__);
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return 0;
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}
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if (!sh_sdhi_intr(host))
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break;
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udelay(1); /* 1 usec */
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}
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return 1; /* Return value: NOT 0 = complete waiting */
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}
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static int sh_sdhi_clock_control(struct sh_sdhi_host *host, unsigned long clk)
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{
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u32 clkdiv, i, timeout;
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if (sh_sdhi_readw(host, SDHI_INFO2) & (1 << 14)) {
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printf(DRIVER_NAME": Busy state ! Cannot change the clock\n");
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return -EBUSY;
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}
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sh_sdhi_writew(host, SDHI_CLK_CTRL,
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~CLK_ENABLE & sh_sdhi_readw(host, SDHI_CLK_CTRL));
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if (clk == 0)
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return -EIO;
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clkdiv = 0x80;
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i = CONFIG_SH_SDHI_FREQ >> (0x8 + 1);
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for (; clkdiv && clk >= (i << 1); (clkdiv >>= 1))
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i <<= 1;
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sh_sdhi_writew(host, SDHI_CLK_CTRL, clkdiv);
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timeout = 100000;
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/* Waiting for SD Bus busy to be cleared */
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while (timeout--) {
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if ((sh_sdhi_readw(host, SDHI_INFO2) & 0x2000))
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break;
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}
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if (timeout)
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sh_sdhi_writew(host, SDHI_CLK_CTRL,
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CLK_ENABLE | sh_sdhi_readw(host, SDHI_CLK_CTRL));
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else
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return -EBUSY;
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return 0;
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}
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static int sh_sdhi_sync_reset(struct sh_sdhi_host *host)
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{
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u32 timeout;
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sh_sdhi_writew(host, SDHI_SOFT_RST, SOFT_RST_ON);
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sh_sdhi_writew(host, SDHI_SOFT_RST, SOFT_RST_OFF);
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sh_sdhi_writew(host, SDHI_CLK_CTRL,
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CLK_ENABLE | sh_sdhi_readw(host, SDHI_CLK_CTRL));
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timeout = 100000;
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while (timeout--) {
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if (!(sh_sdhi_readw(host, SDHI_INFO2) & INFO2_CBUSY))
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break;
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udelay(100);
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}
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if (!timeout)
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return -EBUSY;
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if (host->quirks & SH_SDHI_QUIRK_16BIT_BUF)
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sh_sdhi_writew(host, SDHI_HOST_MODE, 1);
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return 0;
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}
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static int sh_sdhi_error_manage(struct sh_sdhi_host *host)
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{
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unsigned short e_state1, e_state2;
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int ret;
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host->sd_error = 0;
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host->wait_int = 0;
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e_state1 = sh_sdhi_readw(host, SDHI_ERR_STS1);
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e_state2 = sh_sdhi_readw(host, SDHI_ERR_STS2);
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if (e_state2 & ERR_STS2_SYS_ERROR) {
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if (e_state2 & ERR_STS2_RES_STOP_TIMEOUT)
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ret = -ETIMEDOUT;
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else
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ret = -EILSEQ;
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debug("%s: ERR_STS2 = %04x\n",
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DRIVER_NAME, sh_sdhi_readw(host, SDHI_ERR_STS2));
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sh_sdhi_sync_reset(host);
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sh_sdhi_writew(host, SDHI_INFO1_MASK,
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INFO1M_DATA3_CARD_RE | INFO1M_DATA3_CARD_IN);
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return ret;
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}
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if (e_state1 & ERR_STS1_CRC_ERROR || e_state1 & ERR_STS1_CMD_ERROR)
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ret = -EILSEQ;
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else
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ret = -ETIMEDOUT;
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debug("%s: ERR_STS1 = %04x\n",
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DRIVER_NAME, sh_sdhi_readw(host, SDHI_ERR_STS1));
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sh_sdhi_sync_reset(host);
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sh_sdhi_writew(host, SDHI_INFO1_MASK,
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INFO1M_DATA3_CARD_RE | INFO1M_DATA3_CARD_IN);
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return ret;
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}
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static int sh_sdhi_single_read(struct sh_sdhi_host *host, struct mmc_data *data)
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{
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long time;
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unsigned short blocksize, i;
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unsigned short *p = (unsigned short *)data->dest;
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u64 *q = (u64 *)data->dest;
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if ((unsigned long)p & 0x00000001) {
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debug(DRIVER_NAME": %s: The data pointer is unaligned.",
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__func__);
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return -EIO;
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}
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host->wait_int = 0;
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sh_sdhi_writew(host, SDHI_INFO2_MASK,
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~(INFO2M_BRE_ENABLE | INFO2M_BUF_ILL_READ) &
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sh_sdhi_readw(host, SDHI_INFO2_MASK));
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sh_sdhi_writew(host, SDHI_INFO1_MASK,
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~INFO1M_ACCESS_END &
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sh_sdhi_readw(host, SDHI_INFO1_MASK));
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time = sh_sdhi_wait_interrupt_flag(host);
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if (time == 0 || host->sd_error != 0)
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return sh_sdhi_error_manage(host);
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host->wait_int = 0;
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blocksize = sh_sdhi_readw(host, SDHI_SIZE);
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if (host->quirks & SH_SDHI_QUIRK_64BIT_BUF)
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for (i = 0; i < blocksize / 8; i++)
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*q++ = sh_sdhi_readq(host, SDHI_BUF0);
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else
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for (i = 0; i < blocksize / 2; i++)
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*p++ = sh_sdhi_readw(host, SDHI_BUF0);
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time = sh_sdhi_wait_interrupt_flag(host);
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if (time == 0 || host->sd_error != 0)
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return sh_sdhi_error_manage(host);
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host->wait_int = 0;
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return 0;
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}
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static int sh_sdhi_multi_read(struct sh_sdhi_host *host, struct mmc_data *data)
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{
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long time;
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unsigned short blocksize, i, sec;
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unsigned short *p = (unsigned short *)data->dest;
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u64 *q = (u64 *)data->dest;
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if ((unsigned long)p & 0x00000001) {
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debug(DRIVER_NAME": %s: The data pointer is unaligned.",
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__func__);
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return -EIO;
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}
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debug("%s: blocks = %d, blocksize = %d\n",
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__func__, data->blocks, data->blocksize);
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host->wait_int = 0;
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for (sec = 0; sec < data->blocks; sec++) {
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sh_sdhi_writew(host, SDHI_INFO2_MASK,
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~(INFO2M_BRE_ENABLE | INFO2M_BUF_ILL_READ) &
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sh_sdhi_readw(host, SDHI_INFO2_MASK));
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time = sh_sdhi_wait_interrupt_flag(host);
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if (time == 0 || host->sd_error != 0)
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return sh_sdhi_error_manage(host);
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host->wait_int = 0;
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blocksize = sh_sdhi_readw(host, SDHI_SIZE);
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if (host->quirks & SH_SDHI_QUIRK_64BIT_BUF)
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for (i = 0; i < blocksize / 8; i++)
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*q++ = sh_sdhi_readq(host, SDHI_BUF0);
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else
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for (i = 0; i < blocksize / 2; i++)
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*p++ = sh_sdhi_readw(host, SDHI_BUF0);
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}
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return 0;
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}
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static int sh_sdhi_single_write(struct sh_sdhi_host *host,
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struct mmc_data *data)
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{
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long time;
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unsigned short blocksize, i;
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const unsigned short *p = (const unsigned short *)data->src;
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const u64 *q = (const u64 *)data->src;
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if ((unsigned long)p & 0x00000001) {
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debug(DRIVER_NAME": %s: The data pointer is unaligned.",
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__func__);
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return -EIO;
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}
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debug("%s: blocks = %d, blocksize = %d\n",
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__func__, data->blocks, data->blocksize);
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host->wait_int = 0;
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sh_sdhi_writew(host, SDHI_INFO2_MASK,
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~(INFO2M_BWE_ENABLE | INFO2M_BUF_ILL_WRITE) &
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sh_sdhi_readw(host, SDHI_INFO2_MASK));
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sh_sdhi_writew(host, SDHI_INFO1_MASK,
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~INFO1M_ACCESS_END &
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sh_sdhi_readw(host, SDHI_INFO1_MASK));
|
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time = sh_sdhi_wait_interrupt_flag(host);
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if (time == 0 || host->sd_error != 0)
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return sh_sdhi_error_manage(host);
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host->wait_int = 0;
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blocksize = sh_sdhi_readw(host, SDHI_SIZE);
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if (host->quirks & SH_SDHI_QUIRK_64BIT_BUF)
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for (i = 0; i < blocksize / 8; i++)
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sh_sdhi_writeq(host, SDHI_BUF0, *q++);
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else
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for (i = 0; i < blocksize / 2; i++)
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sh_sdhi_writew(host, SDHI_BUF0, *p++);
|
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time = sh_sdhi_wait_interrupt_flag(host);
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if (time == 0 || host->sd_error != 0)
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return sh_sdhi_error_manage(host);
|
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host->wait_int = 0;
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return 0;
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}
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static int sh_sdhi_multi_write(struct sh_sdhi_host *host, struct mmc_data *data)
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{
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long time;
|
unsigned short i, sec, blocksize;
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const unsigned short *p = (const unsigned short *)data->src;
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const u64 *q = (const u64 *)data->src;
|
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debug("%s: blocks = %d, blocksize = %d\n",
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__func__, data->blocks, data->blocksize);
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host->wait_int = 0;
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for (sec = 0; sec < data->blocks; sec++) {
|
sh_sdhi_writew(host, SDHI_INFO2_MASK,
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~(INFO2M_BWE_ENABLE | INFO2M_BUF_ILL_WRITE) &
|
sh_sdhi_readw(host, SDHI_INFO2_MASK));
|
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time = sh_sdhi_wait_interrupt_flag(host);
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if (time == 0 || host->sd_error != 0)
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return sh_sdhi_error_manage(host);
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host->wait_int = 0;
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blocksize = sh_sdhi_readw(host, SDHI_SIZE);
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if (host->quirks & SH_SDHI_QUIRK_64BIT_BUF)
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for (i = 0; i < blocksize / 8; i++)
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sh_sdhi_writeq(host, SDHI_BUF0, *q++);
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else
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for (i = 0; i < blocksize / 2; i++)
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sh_sdhi_writew(host, SDHI_BUF0, *p++);
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}
|
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return 0;
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}
|
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static void sh_sdhi_get_response(struct sh_sdhi_host *host, struct mmc_cmd *cmd)
|
{
|
unsigned short i, j, cnt = 1;
|
unsigned short resp[8];
|
|
if (cmd->resp_type & MMC_RSP_136) {
|
cnt = 4;
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resp[0] = sh_sdhi_readw(host, SDHI_RSP00);
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resp[1] = sh_sdhi_readw(host, SDHI_RSP01);
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resp[2] = sh_sdhi_readw(host, SDHI_RSP02);
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resp[3] = sh_sdhi_readw(host, SDHI_RSP03);
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resp[4] = sh_sdhi_readw(host, SDHI_RSP04);
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resp[5] = sh_sdhi_readw(host, SDHI_RSP05);
|
resp[6] = sh_sdhi_readw(host, SDHI_RSP06);
|
resp[7] = sh_sdhi_readw(host, SDHI_RSP07);
|
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/* SDHI REGISTER SPECIFICATION */
|
for (i = 7, j = 6; i > 0; i--) {
|
resp[i] = (resp[i] << 8) & 0xff00;
|
resp[i] |= (resp[j--] >> 8) & 0x00ff;
|
}
|
resp[0] = (resp[0] << 8) & 0xff00;
|
} else {
|
resp[0] = sh_sdhi_readw(host, SDHI_RSP00);
|
resp[1] = sh_sdhi_readw(host, SDHI_RSP01);
|
}
|
|
#if defined(__BIG_ENDIAN_BITFIELD)
|
if (cnt == 4) {
|
cmd->response[0] = (resp[6] << 16) | resp[7];
|
cmd->response[1] = (resp[4] << 16) | resp[5];
|
cmd->response[2] = (resp[2] << 16) | resp[3];
|
cmd->response[3] = (resp[0] << 16) | resp[1];
|
} else {
|
cmd->response[0] = (resp[0] << 16) | resp[1];
|
}
|
#else
|
if (cnt == 4) {
|
cmd->response[0] = (resp[7] << 16) | resp[6];
|
cmd->response[1] = (resp[5] << 16) | resp[4];
|
cmd->response[2] = (resp[3] << 16) | resp[2];
|
cmd->response[3] = (resp[1] << 16) | resp[0];
|
} else {
|
cmd->response[0] = (resp[1] << 16) | resp[0];
|
}
|
#endif /* __BIG_ENDIAN_BITFIELD */
|
}
|
|
static unsigned short sh_sdhi_set_cmd(struct sh_sdhi_host *host,
|
struct mmc_data *data, unsigned short opc)
|
{
|
if (host->app_cmd) {
|
if (!data)
|
host->app_cmd = 0;
|
return opc | BIT(6);
|
}
|
|
switch (opc) {
|
case MMC_CMD_SWITCH:
|
return opc | (data ? 0x1c00 : 0x40);
|
case MMC_CMD_SEND_EXT_CSD:
|
return opc | (data ? 0x1c00 : 0);
|
case MMC_CMD_SEND_OP_COND:
|
return opc | 0x0700;
|
case MMC_CMD_APP_CMD:
|
host->app_cmd = 1;
|
default:
|
return opc;
|
}
|
}
|
|
static unsigned short sh_sdhi_data_trans(struct sh_sdhi_host *host,
|
struct mmc_data *data, unsigned short opc)
|
{
|
if (host->app_cmd) {
|
host->app_cmd = 0;
|
switch (opc) {
|
case SD_CMD_APP_SEND_SCR:
|
case SD_CMD_APP_SD_STATUS:
|
return sh_sdhi_single_read(host, data);
|
default:
|
printf(DRIVER_NAME": SD: NOT SUPPORT APP CMD = d'%04d\n",
|
opc);
|
return -EINVAL;
|
}
|
} else {
|
switch (opc) {
|
case MMC_CMD_WRITE_MULTIPLE_BLOCK:
|
return sh_sdhi_multi_write(host, data);
|
case MMC_CMD_READ_MULTIPLE_BLOCK:
|
return sh_sdhi_multi_read(host, data);
|
case MMC_CMD_WRITE_SINGLE_BLOCK:
|
return sh_sdhi_single_write(host, data);
|
case MMC_CMD_READ_SINGLE_BLOCK:
|
case MMC_CMD_SWITCH:
|
case MMC_CMD_SEND_EXT_CSD:;
|
return sh_sdhi_single_read(host, data);
|
default:
|
printf(DRIVER_NAME": SD: NOT SUPPORT CMD = d'%04d\n", opc);
|
return -EINVAL;
|
}
|
}
|
}
|
|
static int sh_sdhi_start_cmd(struct sh_sdhi_host *host,
|
struct mmc_data *data, struct mmc_cmd *cmd)
|
{
|
long time;
|
unsigned short shcmd, opc = cmd->cmdidx;
|
int ret = 0;
|
unsigned long timeout;
|
|
debug("opc = %d, arg = %x, resp_type = %x\n",
|
opc, cmd->cmdarg, cmd->resp_type);
|
|
if (opc == MMC_CMD_STOP_TRANSMISSION) {
|
/* SDHI sends the STOP command automatically by STOP reg */
|
sh_sdhi_writew(host, SDHI_INFO1_MASK, ~INFO1M_ACCESS_END &
|
sh_sdhi_readw(host, SDHI_INFO1_MASK));
|
|
time = sh_sdhi_wait_interrupt_flag(host);
|
if (time == 0 || host->sd_error != 0)
|
return sh_sdhi_error_manage(host);
|
|
sh_sdhi_get_response(host, cmd);
|
return 0;
|
}
|
|
if (data) {
|
if ((opc == MMC_CMD_READ_MULTIPLE_BLOCK) ||
|
opc == MMC_CMD_WRITE_MULTIPLE_BLOCK) {
|
sh_sdhi_writew(host, SDHI_STOP, STOP_SEC_ENABLE);
|
sh_sdhi_writew(host, SDHI_SECCNT, data->blocks);
|
}
|
sh_sdhi_writew(host, SDHI_SIZE, data->blocksize);
|
}
|
|
shcmd = sh_sdhi_set_cmd(host, data, opc);
|
|
/*
|
* U-Boot cannot use interrupt.
|
* So this flag may not be clear by timing
|
*/
|
sh_sdhi_writew(host, SDHI_INFO1, ~INFO1_RESP_END);
|
|
sh_sdhi_writew(host, SDHI_INFO1_MASK,
|
INFO1M_RESP_END | sh_sdhi_readw(host, SDHI_INFO1_MASK));
|
sh_sdhi_writew(host, SDHI_ARG0,
|
(unsigned short)(cmd->cmdarg & ARG0_MASK));
|
sh_sdhi_writew(host, SDHI_ARG1,
|
(unsigned short)((cmd->cmdarg >> 16) & ARG1_MASK));
|
|
timeout = 100000;
|
/* Waiting for SD Bus busy to be cleared */
|
while (timeout--) {
|
if ((sh_sdhi_readw(host, SDHI_INFO2) & 0x2000))
|
break;
|
}
|
|
host->wait_int = 0;
|
sh_sdhi_writew(host, SDHI_INFO1_MASK,
|
~INFO1M_RESP_END & sh_sdhi_readw(host, SDHI_INFO1_MASK));
|
sh_sdhi_writew(host, SDHI_INFO2_MASK,
|
~(INFO2M_CMD_ERROR | INFO2M_CRC_ERROR |
|
INFO2M_END_ERROR | INFO2M_TIMEOUT |
|
INFO2M_RESP_TIMEOUT | INFO2M_ILA) &
|
sh_sdhi_readw(host, SDHI_INFO2_MASK));
|
|
sh_sdhi_writew(host, SDHI_CMD, (unsigned short)(shcmd & CMD_MASK));
|
time = sh_sdhi_wait_interrupt_flag(host);
|
if (!time) {
|
host->app_cmd = 0;
|
return sh_sdhi_error_manage(host);
|
}
|
|
if (host->sd_error) {
|
switch (cmd->cmdidx) {
|
case MMC_CMD_ALL_SEND_CID:
|
case MMC_CMD_SELECT_CARD:
|
case SD_CMD_SEND_IF_COND:
|
case MMC_CMD_APP_CMD:
|
ret = -ETIMEDOUT;
|
break;
|
default:
|
debug(DRIVER_NAME": Cmd(d'%d) err\n", opc);
|
debug(DRIVER_NAME": cmdidx = %d\n", cmd->cmdidx);
|
ret = sh_sdhi_error_manage(host);
|
break;
|
}
|
host->sd_error = 0;
|
host->wait_int = 0;
|
host->app_cmd = 0;
|
return ret;
|
}
|
|
if (sh_sdhi_readw(host, SDHI_INFO1) & INFO1_RESP_END) {
|
host->app_cmd = 0;
|
return -EINVAL;
|
}
|
|
if (host->wait_int) {
|
sh_sdhi_get_response(host, cmd);
|
host->wait_int = 0;
|
}
|
|
if (data)
|
ret = sh_sdhi_data_trans(host, data, opc);
|
|
debug("ret = %d, resp = %08x, %08x, %08x, %08x\n",
|
ret, cmd->response[0], cmd->response[1],
|
cmd->response[2], cmd->response[3]);
|
return ret;
|
}
|
|
static int sh_sdhi_send_cmd_common(struct sh_sdhi_host *host,
|
struct mmc_cmd *cmd, struct mmc_data *data)
|
{
|
host->sd_error = 0;
|
|
return sh_sdhi_start_cmd(host, data, cmd);
|
}
|
|
static int sh_sdhi_set_ios_common(struct sh_sdhi_host *host, struct mmc *mmc)
|
{
|
int ret;
|
|
ret = sh_sdhi_clock_control(host, mmc->clock);
|
if (ret)
|
return -EINVAL;
|
|
if (mmc->bus_width == 8)
|
sh_sdhi_writew(host, SDHI_OPTION,
|
OPT_BUS_WIDTH_8 | (~OPT_BUS_WIDTH_M &
|
sh_sdhi_readw(host, SDHI_OPTION)));
|
else if (mmc->bus_width == 4)
|
sh_sdhi_writew(host, SDHI_OPTION,
|
OPT_BUS_WIDTH_4 | (~OPT_BUS_WIDTH_M &
|
sh_sdhi_readw(host, SDHI_OPTION)));
|
else
|
sh_sdhi_writew(host, SDHI_OPTION,
|
OPT_BUS_WIDTH_1 | (~OPT_BUS_WIDTH_M &
|
sh_sdhi_readw(host, SDHI_OPTION)));
|
|
debug("clock = %d, buswidth = %d\n", mmc->clock, mmc->bus_width);
|
|
return 0;
|
}
|
|
static int sh_sdhi_initialize_common(struct sh_sdhi_host *host)
|
{
|
int ret = sh_sdhi_sync_reset(host);
|
|
sh_sdhi_writew(host, SDHI_PORTSEL, USE_1PORT);
|
|
#if defined(__BIG_ENDIAN_BITFIELD)
|
sh_sdhi_writew(host, SDHI_EXT_SWAP, SET_SWAP);
|
#endif
|
|
sh_sdhi_writew(host, SDHI_INFO1_MASK, INFO1M_RESP_END |
|
INFO1M_ACCESS_END | INFO1M_CARD_RE |
|
INFO1M_DATA3_CARD_RE | INFO1M_DATA3_CARD_IN);
|
|
return ret;
|
}
|
|
#ifndef CONFIG_DM_MMC
|
static void *mmc_priv(struct mmc *mmc)
|
{
|
return (void *)mmc->priv;
|
}
|
|
static int sh_sdhi_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
|
struct mmc_data *data)
|
{
|
struct sh_sdhi_host *host = mmc_priv(mmc);
|
|
return sh_sdhi_send_cmd_common(host, cmd, data);
|
}
|
|
static int sh_sdhi_set_ios(struct mmc *mmc)
|
{
|
struct sh_sdhi_host *host = mmc_priv(mmc);
|
|
return sh_sdhi_set_ios_common(host, mmc);
|
}
|
|
static int sh_sdhi_initialize(struct mmc *mmc)
|
{
|
struct sh_sdhi_host *host = mmc_priv(mmc);
|
|
return sh_sdhi_initialize_common(host);
|
}
|
|
static const struct mmc_ops sh_sdhi_ops = {
|
.send_cmd = sh_sdhi_send_cmd,
|
.set_ios = sh_sdhi_set_ios,
|
.init = sh_sdhi_initialize,
|
};
|
|
#ifdef CONFIG_RCAR_GEN3
|
static struct mmc_config sh_sdhi_cfg = {
|
.name = DRIVER_NAME,
|
.ops = &sh_sdhi_ops,
|
.f_min = CLKDEV_INIT,
|
.f_max = CLKDEV_HS_DATA,
|
.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
|
.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HS |
|
MMC_MODE_HS_52MHz,
|
.part_type = PART_TYPE_DOS,
|
.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
|
};
|
#else
|
static struct mmc_config sh_sdhi_cfg = {
|
.name = DRIVER_NAME,
|
.ops = &sh_sdhi_ops,
|
.f_min = CLKDEV_INIT,
|
.f_max = CLKDEV_HS_DATA,
|
.voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
|
.host_caps = MMC_MODE_4BIT | MMC_MODE_HS,
|
.part_type = PART_TYPE_DOS,
|
.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
|
};
|
#endif
|
|
int sh_sdhi_init(unsigned long addr, int ch, unsigned long quirks)
|
{
|
int ret = 0;
|
struct mmc *mmc;
|
struct sh_sdhi_host *host = NULL;
|
|
if (ch >= CONFIG_SYS_SH_SDHI_NR_CHANNEL)
|
return -ENODEV;
|
|
host = malloc(sizeof(struct sh_sdhi_host));
|
if (!host)
|
return -ENOMEM;
|
|
mmc = mmc_create(&sh_sdhi_cfg, host);
|
if (!mmc) {
|
ret = -1;
|
goto error;
|
}
|
|
host->ch = ch;
|
host->addr = (void __iomem *)addr;
|
host->quirks = quirks;
|
|
if (host->quirks & SH_SDHI_QUIRK_64BIT_BUF)
|
host->bus_shift = 2;
|
else if (host->quirks & SH_SDHI_QUIRK_16BIT_BUF)
|
host->bus_shift = 1;
|
|
return ret;
|
error:
|
if (host)
|
free(host);
|
return ret;
|
}
|
|
#else
|
|
struct sh_sdhi_plat {
|
struct mmc_config cfg;
|
struct mmc mmc;
|
};
|
|
int sh_sdhi_dm_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
|
struct mmc_data *data)
|
{
|
struct sh_sdhi_host *host = dev_get_priv(dev);
|
|
return sh_sdhi_send_cmd_common(host, cmd, data);
|
}
|
|
int sh_sdhi_dm_set_ios(struct udevice *dev)
|
{
|
struct sh_sdhi_host *host = dev_get_priv(dev);
|
struct mmc *mmc = mmc_get_mmc_dev(dev);
|
|
return sh_sdhi_set_ios_common(host, mmc);
|
}
|
|
static const struct dm_mmc_ops sh_sdhi_dm_ops = {
|
.send_cmd = sh_sdhi_dm_send_cmd,
|
.set_ios = sh_sdhi_dm_set_ios,
|
};
|
|
static int sh_sdhi_dm_bind(struct udevice *dev)
|
{
|
struct sh_sdhi_plat *plat = dev_get_platdata(dev);
|
|
return mmc_bind(dev, &plat->mmc, &plat->cfg);
|
}
|
|
static int sh_sdhi_dm_probe(struct udevice *dev)
|
{
|
struct sh_sdhi_plat *plat = dev_get_platdata(dev);
|
struct sh_sdhi_host *host = dev_get_priv(dev);
|
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
|
struct clk sh_sdhi_clk;
|
const u32 quirks = dev_get_driver_data(dev);
|
fdt_addr_t base;
|
int ret;
|
|
base = devfdt_get_addr(dev);
|
if (base == FDT_ADDR_T_NONE)
|
return -EINVAL;
|
|
host->addr = devm_ioremap(dev, base, SZ_2K);
|
if (!host->addr)
|
return -ENOMEM;
|
|
ret = clk_get_by_index(dev, 0, &sh_sdhi_clk);
|
if (ret) {
|
debug("failed to get clock, ret=%d\n", ret);
|
return ret;
|
}
|
|
ret = clk_enable(&sh_sdhi_clk);
|
if (ret) {
|
debug("failed to enable clock, ret=%d\n", ret);
|
return ret;
|
}
|
|
host->quirks = quirks;
|
|
if (host->quirks & SH_SDHI_QUIRK_64BIT_BUF)
|
host->bus_shift = 2;
|
else if (host->quirks & SH_SDHI_QUIRK_16BIT_BUF)
|
host->bus_shift = 1;
|
|
plat->cfg.name = dev->name;
|
plat->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
|
|
switch (fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "bus-width",
|
1)) {
|
case 8:
|
plat->cfg.host_caps |= MMC_MODE_8BIT;
|
break;
|
case 4:
|
plat->cfg.host_caps |= MMC_MODE_4BIT;
|
break;
|
case 1:
|
break;
|
default:
|
dev_err(dev, "Invalid \"bus-width\" value\n");
|
return -EINVAL;
|
}
|
|
sh_sdhi_initialize_common(host);
|
|
plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
|
plat->cfg.f_min = CLKDEV_INIT;
|
plat->cfg.f_max = CLKDEV_HS_DATA;
|
plat->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
|
|
upriv->mmc = &plat->mmc;
|
|
return 0;
|
}
|
|
static const struct udevice_id sh_sdhi_sd_match[] = {
|
{ .compatible = "renesas,sdhi-r8a7795", .data = SH_SDHI_QUIRK_64BIT_BUF },
|
{ .compatible = "renesas,sdhi-r8a7796", .data = SH_SDHI_QUIRK_64BIT_BUF },
|
{ /* sentinel */ }
|
};
|
|
U_BOOT_DRIVER(sh_sdhi_mmc) = {
|
.name = "sh-sdhi-mmc",
|
.id = UCLASS_MMC,
|
.of_match = sh_sdhi_sd_match,
|
.bind = sh_sdhi_dm_bind,
|
.probe = sh_sdhi_dm_probe,
|
.priv_auto_alloc_size = sizeof(struct sh_sdhi_host),
|
.platdata_auto_alloc_size = sizeof(struct sh_sdhi_plat),
|
.ops = &sh_sdhi_dm_ops,
|
};
|
#endif
|
