/*
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* (C) Copyright 2016 Fuzhou Rockchip Electronics Co., Ltd
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*
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* Rockchip SD Host Controller Interface
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/arch/hardware.h>
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#include <common.h>
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#include <dm.h>
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#include <dt-structs.h>
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#include <linux/libfdt.h>
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#include <malloc.h>
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#include <mapmem.h>
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#include <sdhci.h>
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#include <clk.h>
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#include <syscon.h>
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#include <dm/ofnode.h>
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#include <asm/arch/clock.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* 400KHz is max freq for card ID etc. Use that as min */
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#define EMMC_MIN_FREQ 400000
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#define KHz (1000)
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#define MHz (1000 * KHz)
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#define PHYCTRL_CALDONE_MASK 0x1
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#define PHYCTRL_CALDONE_SHIFT 0x6
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#define PHYCTRL_CALDONE_DONE 0x1
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#define PHYCTRL_DLLRDY_MASK 0x1
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#define PHYCTRL_DLLRDY_SHIFT 0x5
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#define PHYCTRL_DLLRDY_DONE 0x1
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#define PHYCTRL_FREQSEL_200M 0x0
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#define PHYCTRL_FREQSEL_50M 0x1
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#define PHYCTRL_FREQSEL_100M 0x2
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#define PHYCTRL_FREQSEL_150M 0x3
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#define PHYCTRL_DLL_LOCK_WO_TMOUT(x) \
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((((x) >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK) ==\
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PHYCTRL_DLLRDY_DONE)
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/* Rockchip specific Registers */
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#define DWCMSHC_CTRL_HS400 0x7
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#define DWCMSHC_CARD_IS_EMMC BIT(0)
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#define DWCMSHC_ENHANCED_STROBE BIT(8)
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#define DWCMSHC_HOST_CTRL3 0x508
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#define DWCMSHC_EMMC_CONTROL 0x52c
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#define DWCMSHC_EMMC_DLL_CTRL 0x800
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#define DWCMSHC_EMMC_DLL_CTRL_RESET BIT(1)
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#define DWCMSHC_EMMC_DLL_RXCLK 0x804
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#define DWCMSHC_EMMC_DLL_TXCLK 0x808
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#define DWCMSHC_EMMC_DLL_STRBIN 0x80c
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#define DECMSHC_EMMC_DLL_CMDOUT 0x810
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#define DWCMSHC_EMMC_DLL_STATUS0 0x840
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#define DWCMSHC_EMMC_DLL_STATUS1 0x844
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#define DWCMSHC_EMMC_DLL_START BIT(0)
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#define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL 29
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#define DWCMSHC_EMMC_DLL_START_POINT 16
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#define DWCMSHC_EMMC_DLL_START_DEFAULT 5
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#define DWCMSHC_EMMC_DLL_INC_VALUE 2
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#define DWCMSHC_EMMC_DLL_INC 8
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#define DWCMSHC_EMMC_DLL_DLYENA BIT(27)
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#define DLL_TXCLK_TAPNUM_DEFAULT 0x10
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#define DLL_TXCLK_TAPNUM_90_DEGREES 0x8
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#define DLL_STRBIN_TAPNUM_DEFAULT 0x3
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#define DLL_TXCLK_TAPNUM_FROM_SW BIT(24)
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#define DLL_TXCLK_NO_INVERTER BIT(29)
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#define DWCMSHC_EMMC_DLL_LOCKED BIT(8)
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#define DWCMSHC_EMMC_DLL_TIMEOUT BIT(9)
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#define DLL_RXCLK_NO_INVERTER 1
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#define DLL_RXCLK_INVERTER 0
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#define DLL_CMDOUT_TAPNUM_90_DEGREES 0x8
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#define DLL_CMDOUT_TAPNUM_FROM_SW BIT(24)
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#define DLL_CMDOUT_SRC_CLK_NEG BIT(28)
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#define DLL_CMDOUT_EN_SRC_CLK_NEG BIT(29)
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#define DWCMSHC_ENHANCED_STROBE BIT(8)
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#define DLL_LOCK_WO_TMOUT(x) \
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((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \
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(((x) & DWCMSHC_EMMC_DLL_TIMEOUT) == 0))
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#define ROCKCHIP_MAX_CLKS 3
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struct rockchip_sdhc_plat {
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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struct dtd_rockchip_rk3399_sdhci_5_1 dtplat;
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#endif
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struct mmc_config cfg;
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struct mmc mmc;
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};
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struct rockchip_emmc_phy {
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u32 emmcphy_con[7];
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u32 reserved;
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u32 emmcphy_status;
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};
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struct rockchip_sdhc {
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struct sdhci_host host;
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struct udevice *dev;
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void *base;
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struct rockchip_emmc_phy *phy;
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struct clk emmc_clk;
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};
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struct sdhci_data {
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int (*emmc_set_clock)(struct sdhci_host *host, unsigned int clock);
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void (*set_ios_post)(struct sdhci_host *host);
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int (*get_phy)(struct udevice *dev);
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u32 flags;
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#define RK_DLL_CMD_OUT BIT(1)
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#define RK_RXCLK_NO_INVERTER BIT(2)
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};
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static void rk3399_emmc_phy_power_on(struct rockchip_emmc_phy *phy, u32 clock)
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{
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u32 caldone, dllrdy, freqsel;
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uint start;
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writel(RK_CLRSETBITS(7 << 4, 0), &phy->emmcphy_con[6]);
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writel(RK_CLRSETBITS(1 << 11, 1 << 11), &phy->emmcphy_con[0]);
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writel(RK_CLRSETBITS(0xf << 7, 6 << 7), &phy->emmcphy_con[0]);
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/*
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* According to the user manual, calpad calibration
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* cycle takes more than 2us without the minimal recommended
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* value, so we may need a little margin here
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*/
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udelay(3);
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writel(RK_CLRSETBITS(1, 1), &phy->emmcphy_con[6]);
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/*
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* According to the user manual, it asks driver to
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* wait 5us for calpad busy trimming. But it seems that
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* 5us of caldone isn't enough for all cases.
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*/
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udelay(500);
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caldone = readl(&phy->emmcphy_status);
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caldone = (caldone >> PHYCTRL_CALDONE_SHIFT) & PHYCTRL_CALDONE_MASK;
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if (caldone != PHYCTRL_CALDONE_DONE) {
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printf("%s: caldone timeout.\n", __func__);
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return;
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}
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/* Set the frequency of the DLL operation */
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if (clock < 75 * MHz)
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freqsel = PHYCTRL_FREQSEL_50M;
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else if (clock < 125 * MHz)
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freqsel = PHYCTRL_FREQSEL_100M;
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else if (clock < 175 * MHz)
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freqsel = PHYCTRL_FREQSEL_150M;
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else
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freqsel = PHYCTRL_FREQSEL_200M;
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/* Set the frequency of the DLL operation */
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writel(RK_CLRSETBITS(3 << 12, freqsel << 12), &phy->emmcphy_con[0]);
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writel(RK_CLRSETBITS(1 << 1, 1 << 1), &phy->emmcphy_con[6]);
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/* REN Enable on STRB Line for HS400 */
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writel(RK_CLRSETBITS(0, 1 << 9), &phy->emmcphy_con[2]);
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start = get_timer(0);
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do {
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udelay(1);
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dllrdy = readl(&phy->emmcphy_status);
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dllrdy = (dllrdy >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK;
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if (dllrdy == PHYCTRL_DLLRDY_DONE)
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break;
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} while (get_timer(start) < 50000);
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if (dllrdy != PHYCTRL_DLLRDY_DONE)
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printf("%s: dllrdy timeout.\n", __func__);
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}
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static void rk3399_emmc_phy_power_off(struct rockchip_emmc_phy *phy)
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{
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writel(RK_CLRSETBITS(1, 0), &phy->emmcphy_con[6]);
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writel(RK_CLRSETBITS(1 << 1, 0), &phy->emmcphy_con[6]);
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}
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static int rockchip_emmc_set_clock(struct sdhci_host *host, unsigned int clock)
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{
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unsigned int div, clk = 0, timeout;
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unsigned int input_clk;
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struct rockchip_sdhc *priv =
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container_of(host, struct rockchip_sdhc, host);
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/* Wait max 20 ms */
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timeout = 200;
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while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
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(SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
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if (timeout == 0) {
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printf("%s: Timeout to wait cmd & data inhibit\n",
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__func__);
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return -EBUSY;
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}
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timeout--;
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udelay(100);
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}
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sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
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if (clock == 0)
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return 0;
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input_clk = clk_set_rate(&priv->emmc_clk, clock);
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if (IS_ERR_VALUE(input_clk))
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input_clk = host->max_clk;
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if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
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/*
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* Check if the Host Controller supports Programmable Clock
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* Mode.
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*/
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if (host->clk_mul) {
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for (div = 1; div <= 1024; div++) {
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if ((input_clk / div) <= clock)
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break;
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}
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/*
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* Set Programmable Clock Mode in the Clock
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* Control register.
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*/
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clk = SDHCI_PROG_CLOCK_MODE;
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div--;
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} else {
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/* Version 3.00 divisors must be a multiple of 2. */
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if (input_clk <= clock) {
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div = 1;
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} else {
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for (div = 2;
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div < SDHCI_MAX_DIV_SPEC_300;
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div += 2) {
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if ((input_clk / div) <= clock)
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break;
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}
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}
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div >>= 1;
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}
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} else {
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/* Version 2.00 divisors must be a power of 2. */
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for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
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if ((input_clk / div) <= clock)
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break;
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}
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div >>= 1;
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}
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clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
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clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
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<< SDHCI_DIVIDER_HI_SHIFT;
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clk |= SDHCI_CLOCK_INT_EN;
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sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
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/* Wait max 20 ms */
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timeout = 20;
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while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
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& SDHCI_CLOCK_INT_STABLE)) {
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if (timeout == 0) {
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printf("%s: Internal clock never stabilised.\n",
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__func__);
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return -EBUSY;
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}
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timeout--;
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udelay(1000);
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}
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clk |= SDHCI_CLOCK_CARD_EN;
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sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
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host->clock = clock;
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return 0;
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}
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static int rk3399_emmc_get_phy(struct udevice *dev)
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{
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struct rockchip_sdhc *priv = dev_get_priv(dev);
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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priv->phy = (struct rockchip_emmc_phy *)0xff77f780;
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#else
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ofnode phy_node;
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void *grf_base;
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u32 grf_phy_offset, phandle;
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phandle = dev_read_u32_default(dev, "phys", 0);
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phy_node = ofnode_get_by_phandle(phandle);
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if (!ofnode_valid(phy_node)) {
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debug("Not found emmc phy device\n");
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return -ENODEV;
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}
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grf_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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if (IS_ERR(grf_base))
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printf("%s Get syscon grf failed", __func__);
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grf_phy_offset = ofnode_read_u32_default(phy_node, "reg", 0);
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priv->phy = (struct rockchip_emmc_phy *)(grf_base + grf_phy_offset);
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#endif
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return 0;
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}
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static int rk3399_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned int clock)
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{
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struct rockchip_sdhc *priv =
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container_of(host, struct rockchip_sdhc, host);
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int cycle_phy = host->clock != clock &&
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clock > EMMC_MIN_FREQ;
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if (cycle_phy)
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rk3399_emmc_phy_power_off(priv->phy);
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rockchip_emmc_set_clock(host, clock);
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if (cycle_phy)
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rk3399_emmc_phy_power_on(priv->phy, clock);
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return 0;
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}
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static int dwcmshc_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned int clock)
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{
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struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
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struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev);
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u32 extra;
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int timeout = 500, ret;
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ret = rockchip_emmc_set_clock(host, clock);
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if (clock >= 100 * MHz) {
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/* reset DLL */
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sdhci_writel(host, DWCMSHC_EMMC_DLL_CTRL_RESET, DWCMSHC_EMMC_DLL_CTRL);
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udelay(1);
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sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
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/* Init DLL settings */
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extra = DWCMSHC_EMMC_DLL_START_DEFAULT << DWCMSHC_EMMC_DLL_START_POINT |
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DWCMSHC_EMMC_DLL_INC_VALUE << DWCMSHC_EMMC_DLL_INC |
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DWCMSHC_EMMC_DLL_START;
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sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL);
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while (1) {
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if (timeout < 0)
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return -ETIMEDOUT;
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if (DLL_LOCK_WO_TMOUT((sdhci_readl(host, DWCMSHC_EMMC_DLL_STATUS0))))
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break;
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udelay(1);
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timeout--;
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}
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extra = DWCMSHC_EMMC_DLL_DLYENA;
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if (data->flags & RK_RXCLK_NO_INVERTER)
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extra |= DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL;
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sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
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extra = DWCMSHC_EMMC_DLL_DLYENA |
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DLL_TXCLK_TAPNUM_FROM_SW |
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DLL_TXCLK_NO_INVERTER|
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DLL_TXCLK_TAPNUM_DEFAULT;
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sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK);
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extra = DWCMSHC_EMMC_DLL_DLYENA |
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DLL_STRBIN_TAPNUM_DEFAULT;
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sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
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} else {
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/* Disable cmd conflict check */
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extra = sdhci_readl(host, DWCMSHC_HOST_CTRL3);
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extra &= ~BIT(0);
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sdhci_writel(host, extra, DWCMSHC_HOST_CTRL3);
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/* reset the clock phase when the frequency is lower than 100MHz */
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sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
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sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_RXCLK);
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sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
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sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN);
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sdhci_writel(host, 0, DECMSHC_EMMC_DLL_CMDOUT);
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}
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return ret;
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}
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static void dwcmshc_sdhci_set_ios_post(struct sdhci_host *host)
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{
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u16 ctrl;
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u32 extra;
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u32 timing = host->mmc->timing;
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if (timing == MMC_TIMING_MMC_HS400 || timing == MMC_TIMING_MMC_HS400ES) {
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ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
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ctrl &= ~SDHCI_CTRL_UHS_MASK;
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ctrl |= DWCMSHC_CTRL_HS400;
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sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
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/* set CARD_IS_EMMC bit to enable Data Strobe for HS400 */
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ctrl = sdhci_readw(host, DWCMSHC_EMMC_CONTROL);
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ctrl |= DWCMSHC_CARD_IS_EMMC;
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sdhci_writew(host, ctrl, DWCMSHC_EMMC_CONTROL);
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extra = DLL_CMDOUT_SRC_CLK_NEG |
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DLL_CMDOUT_EN_SRC_CLK_NEG;
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sdhci_writel(host, extra, DECMSHC_EMMC_DLL_CMDOUT);
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extra = DWCMSHC_EMMC_DLL_DLYENA |
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DLL_TXCLK_TAPNUM_FROM_SW |
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DLL_TXCLK_NO_INVERTER|
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DLL_TXCLK_TAPNUM_90_DEGREES;
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sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK);
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}
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}
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static int dwcmshc_emmc_get_phy(struct udevice *dev)
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{
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return 0;
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}
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static int rockchip_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
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{
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struct rockchip_sdhc *priv =
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container_of(host, struct rockchip_sdhc, host);
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struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev);
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if (!data)
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return -EINVAL;
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return data->emmc_set_clock(host, clock);
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}
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static void rockchip_sdhci_set_ios_post(struct sdhci_host *host)
|
{
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struct rockchip_sdhc *priv =
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container_of(host, struct rockchip_sdhc, host);
|
struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev);
|
|
if (data && data->set_ios_post)
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data->set_ios_post(host);
|
}
|
|
static struct sdhci_ops rockchip_sdhci_ops = {
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.set_clock = rockchip_sdhci_set_clock,
|
.set_ios_post = rockchip_sdhci_set_ios_post,
|
};
|
|
static int rockchip_sdhci_probe(struct udevice *dev)
|
{
|
struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(dev);
|
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
|
struct rockchip_sdhc_plat *plat = dev_get_platdata(dev);
|
struct rockchip_sdhc *prv = dev_get_priv(dev);
|
struct sdhci_host *host = &prv->host;
|
int max_frequency, ret;
|
struct clk clk;
|
|
#if CONFIG_IS_ENABLED(OF_PLATDATA)
|
struct dtd_rockchip_rk3399_sdhci_5_1 *dtplat = &plat->dtplat;
|
|
host->name = dev->name;
|
host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
|
host->host_caps |= MMC_MODE_8BIT;
|
max_frequency = dtplat->max_frequency;
|
ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &clk);
|
#else
|
max_frequency = dev_read_u32_default(dev, "max-frequency", 0);
|
switch (dev_read_u32_default(dev, "bus-width", 4)) {
|
case 8:
|
host->host_caps |= MMC_MODE_8BIT;
|
break;
|
case 4:
|
host->host_caps |= MMC_MODE_4BIT;
|
break;
|
case 1:
|
break;
|
default:
|
printf("Invalid \"bus-width\" value\n");
|
return -EINVAL;
|
}
|
ret = clk_get_by_index(dev, 0, &clk);
|
#endif
|
if (!ret) {
|
ret = clk_set_rate(&clk, max_frequency);
|
if (IS_ERR_VALUE(ret))
|
printf("%s clk set rate fail!\n", __func__);
|
} else {
|
printf("%s fail to get clk\n", __func__);
|
}
|
|
prv->emmc_clk = clk;
|
prv->dev = dev;
|
ret = data->get_phy(dev);
|
if (ret)
|
return ret;
|
|
host->ops = &rockchip_sdhci_ops;
|
|
host->max_clk = max_frequency;
|
|
if (dev_read_bool(dev, "mmc-hs200-1_8v"))
|
host->host_caps |= MMC_MODE_HS200;
|
else if (dev_read_bool(dev, "mmc-hs400-1_8v"))
|
host->host_caps |= MMC_MODE_HS400;
|
ret = sdhci_setup_cfg(&plat->cfg, host, 0, EMMC_MIN_FREQ);
|
|
host->mmc = &plat->mmc;
|
if (ret)
|
return ret;
|
host->mmc->priv = &prv->host;
|
host->mmc->dev = dev;
|
upriv->mmc = host->mmc;
|
|
return sdhci_probe(dev);
|
}
|
|
static int rockchip_sdhci_of_to_plat(struct udevice *dev)
|
{
|
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
|
struct sdhci_host *host = dev_get_priv(dev);
|
|
host->name = dev->name;
|
host->ioaddr = dev_read_addr_ptr(dev);
|
#endif
|
|
return 0;
|
}
|
|
static int rockchip_sdhci_bind(struct udevice *dev)
|
{
|
struct rockchip_sdhc_plat *plat = dev_get_platdata(dev);
|
|
return sdhci_bind(dev, &plat->mmc, &plat->cfg);
|
}
|
|
static const struct sdhci_data arasan_data = {
|
.emmc_set_clock = rk3399_sdhci_emmc_set_clock,
|
.get_phy = rk3399_emmc_get_phy,
|
};
|
|
static const struct sdhci_data rk3568_data = {
|
.emmc_set_clock = dwcmshc_sdhci_emmc_set_clock,
|
.get_phy = dwcmshc_emmc_get_phy,
|
.flags = RK_RXCLK_NO_INVERTER,
|
};
|
|
static const struct sdhci_data rk3588_data = {
|
.emmc_set_clock = dwcmshc_sdhci_emmc_set_clock,
|
.get_phy = dwcmshc_emmc_get_phy,
|
.set_ios_post = dwcmshc_sdhci_set_ios_post,
|
.flags = RK_DLL_CMD_OUT | RK_RXCLK_NO_INVERTER,
|
};
|
|
static const struct udevice_id sdhci_ids[] = {
|
{
|
.compatible = "arasan,sdhci-5.1",
|
.data = (ulong)&arasan_data,
|
},
|
{
|
.compatible = "snps,dwcmshc-sdhci",
|
.data = (ulong)&rk3568_data,
|
},
|
{
|
.compatible = "rockchip,rk3588-dwcmshc",
|
.data = (ulong)&rk3588_data,
|
},
|
{ }
|
};
|
|
U_BOOT_DRIVER(arasan_sdhci_drv) = {
|
.name = "rockchip_sdhci_5_1",
|
.id = UCLASS_MMC,
|
.of_match = sdhci_ids,
|
.ofdata_to_platdata = rockchip_sdhci_of_to_plat,
|
.ops = &sdhci_ops,
|
.bind = rockchip_sdhci_bind,
|
.probe = rockchip_sdhci_probe,
|
.priv_auto_alloc_size = sizeof(struct rockchip_sdhc),
|
.platdata_auto_alloc_size = sizeof(struct rockchip_sdhc_plat),
|
};
|
