/*
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* (C) Copyright 2008
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* Texas Instruments, <www.ti.com>
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* Sukumar Ghorai <s-ghorai@ti.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation's version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <common.h>
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#include <malloc.h>
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#include <mmc.h>
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#include <part.h>
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#include <i2c.h>
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#include <twl4030.h>
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#include <twl6030.h>
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#include <palmas.h>
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#include <asm/io.h>
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#include <asm/arch/mmc_host_def.h>
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#if !defined(CONFIG_SOC_KEYSTONE)
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#include <asm/gpio.h>
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#include <asm/arch/sys_proto.h>
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#endif
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#ifdef CONFIG_MMC_OMAP36XX_PINS
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#include <asm/arch/mux.h>
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#endif
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#include <dm.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* simplify defines to OMAP_HSMMC_USE_GPIO */
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#if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
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(defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
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#define OMAP_HSMMC_USE_GPIO
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#else
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#undef OMAP_HSMMC_USE_GPIO
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#endif
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/* common definitions for all OMAPs */
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#define SYSCTL_SRC (1 << 25)
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#define SYSCTL_SRD (1 << 26)
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struct omap2_mmc_platform_config {
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u32 reg_offset;
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};
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struct omap_hsmmc_data {
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struct hsmmc *base_addr;
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#if !CONFIG_IS_ENABLED(DM_MMC)
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struct mmc_config cfg;
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#endif
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#ifdef OMAP_HSMMC_USE_GPIO
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#if CONFIG_IS_ENABLED(DM_MMC)
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struct gpio_desc cd_gpio; /* Change Detect GPIO */
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struct gpio_desc wp_gpio; /* Write Protect GPIO */
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bool cd_inverted;
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#else
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int cd_gpio;
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int wp_gpio;
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#endif
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#endif
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};
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/* If we fail after 1 second wait, something is really bad */
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#define MAX_RETRY_MS 1000
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static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
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static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
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unsigned int siz);
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static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc)
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{
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#if CONFIG_IS_ENABLED(DM_MMC)
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return dev_get_priv(mmc->dev);
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#else
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return (struct omap_hsmmc_data *)mmc->priv;
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#endif
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}
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static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc)
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{
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#if CONFIG_IS_ENABLED(DM_MMC)
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struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev);
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return &plat->cfg;
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#else
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return &((struct omap_hsmmc_data *)mmc->priv)->cfg;
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#endif
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}
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#if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC)
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static int omap_mmc_setup_gpio_in(int gpio, const char *label)
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{
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int ret;
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#ifndef CONFIG_DM_GPIO
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if (!gpio_is_valid(gpio))
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return -1;
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#endif
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ret = gpio_request(gpio, label);
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if (ret)
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return ret;
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ret = gpio_direction_input(gpio);
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if (ret)
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return ret;
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return gpio;
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}
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#endif
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static unsigned char mmc_board_init(struct mmc *mmc)
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{
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#if defined(CONFIG_OMAP34XX)
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struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
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t2_t *t2_base = (t2_t *)T2_BASE;
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struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
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u32 pbias_lite;
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#ifdef CONFIG_MMC_OMAP36XX_PINS
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u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
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#endif
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pbias_lite = readl(&t2_base->pbias_lite);
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pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
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#ifdef CONFIG_TARGET_OMAP3_CAIRO
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/* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
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pbias_lite &= ~PBIASLITEVMODE0;
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#endif
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#ifdef CONFIG_MMC_OMAP36XX_PINS
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if (get_cpu_family() == CPU_OMAP36XX) {
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/* Disable extended drain IO before changing PBIAS */
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wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
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writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
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}
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#endif
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writel(pbias_lite, &t2_base->pbias_lite);
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writel(pbias_lite | PBIASLITEPWRDNZ1 |
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PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
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&t2_base->pbias_lite);
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#ifdef CONFIG_MMC_OMAP36XX_PINS
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if (get_cpu_family() == CPU_OMAP36XX)
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/* Enable extended drain IO after changing PBIAS */
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writel(wkup_ctrl |
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OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
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OMAP34XX_CTRL_WKUP_CTRL);
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#endif
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writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
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&t2_base->devconf0);
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writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
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&t2_base->devconf1);
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/* Change from default of 52MHz to 26MHz if necessary */
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if (!(cfg->host_caps & MMC_MODE_HS_52MHz))
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writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
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&t2_base->ctl_prog_io1);
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writel(readl(&prcm_base->fclken1_core) |
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EN_MMC1 | EN_MMC2 | EN_MMC3,
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&prcm_base->fclken1_core);
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writel(readl(&prcm_base->iclken1_core) |
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EN_MMC1 | EN_MMC2 | EN_MMC3,
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&prcm_base->iclken1_core);
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#endif
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#if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
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/* PBIAS config needed for MMC1 only */
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if (mmc_get_blk_desc(mmc)->devnum == 0)
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vmmc_pbias_config(LDO_VOLT_3V0);
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#endif
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return 0;
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}
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void mmc_init_stream(struct hsmmc *mmc_base)
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{
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ulong start;
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writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
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writel(MMC_CMD0, &mmc_base->cmd);
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start = get_timer(0);
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while (!(readl(&mmc_base->stat) & CC_MASK)) {
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if (get_timer(0) - start > MAX_RETRY_MS) {
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printf("%s: timedout waiting for cc!\n", __func__);
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return;
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}
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}
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writel(CC_MASK, &mmc_base->stat)
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;
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writel(MMC_CMD0, &mmc_base->cmd)
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;
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start = get_timer(0);
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while (!(readl(&mmc_base->stat) & CC_MASK)) {
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if (get_timer(0) - start > MAX_RETRY_MS) {
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printf("%s: timedout waiting for cc2!\n", __func__);
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return;
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}
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}
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writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
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}
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static int omap_hsmmc_init_setup(struct mmc *mmc)
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{
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struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
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struct hsmmc *mmc_base;
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unsigned int reg_val;
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unsigned int dsor;
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ulong start;
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mmc_base = priv->base_addr;
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mmc_board_init(mmc);
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writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
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&mmc_base->sysconfig);
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start = get_timer(0);
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while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
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if (get_timer(0) - start > MAX_RETRY_MS) {
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printf("%s: timedout waiting for cc2!\n", __func__);
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return -ETIMEDOUT;
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}
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}
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writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
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start = get_timer(0);
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while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
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if (get_timer(0) - start > MAX_RETRY_MS) {
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printf("%s: timedout waiting for softresetall!\n",
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__func__);
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return -ETIMEDOUT;
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}
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}
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writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
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writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
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&mmc_base->capa);
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reg_val = readl(&mmc_base->con) & RESERVED_MASK;
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writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
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MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
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HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
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dsor = 240;
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mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
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(ICE_STOP | DTO_15THDTO | CEN_DISABLE));
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mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
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(dsor << CLKD_OFFSET) | ICE_OSCILLATE);
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start = get_timer(0);
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while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
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if (get_timer(0) - start > MAX_RETRY_MS) {
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printf("%s: timedout waiting for ics!\n", __func__);
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return -ETIMEDOUT;
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}
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}
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writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
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writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
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writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
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IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC,
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&mmc_base->ie);
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mmc_init_stream(mmc_base);
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return 0;
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}
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/*
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* MMC controller internal finite state machine reset
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*
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* Used to reset command or data internal state machines, using respectively
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* SRC or SRD bit of SYSCTL register
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*/
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static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
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{
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ulong start;
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mmc_reg_out(&mmc_base->sysctl, bit, bit);
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/*
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* CMD(DAT) lines reset procedures are slightly different
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* for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
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* According to OMAP3 TRM:
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* Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
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* returns to 0x0.
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* According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
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* procedure steps must be as follows:
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* 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
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* MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
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* 2. Poll the SRC(SRD) bit until it is set to 0x1.
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* 3. Wait until the SRC (SRD) bit returns to 0x0
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* (reset procedure is completed).
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*/
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#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
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defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
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if (!(readl(&mmc_base->sysctl) & bit)) {
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start = get_timer(0);
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while (!(readl(&mmc_base->sysctl) & bit)) {
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if (get_timer(0) - start > MAX_RETRY_MS)
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return;
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}
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}
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#endif
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start = get_timer(0);
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while ((readl(&mmc_base->sysctl) & bit) != 0) {
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if (get_timer(0) - start > MAX_RETRY_MS) {
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printf("%s: timedout waiting for sysctl %x to clear\n",
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__func__, bit);
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return;
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}
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}
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}
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#if !CONFIG_IS_ENABLED(DM_MMC)
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static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
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struct mmc_data *data)
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{
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struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
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#else
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static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
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struct mmc_data *data)
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{
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struct omap_hsmmc_data *priv = dev_get_priv(dev);
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#endif
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struct hsmmc *mmc_base;
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unsigned int flags, mmc_stat;
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ulong start;
|
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mmc_base = priv->base_addr;
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start = get_timer(0);
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while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
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if (get_timer(0) - start > MAX_RETRY_MS) {
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printf("%s: timedout waiting on cmd inhibit to clear\n",
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__func__);
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return -ETIMEDOUT;
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}
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}
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writel(0xFFFFFFFF, &mmc_base->stat);
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start = get_timer(0);
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while (readl(&mmc_base->stat)) {
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if (get_timer(0) - start > MAX_RETRY_MS) {
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printf("%s: timedout waiting for STAT (%x) to clear\n",
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__func__, readl(&mmc_base->stat));
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return -ETIMEDOUT;
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}
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}
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/*
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* CMDREG
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* CMDIDX[13:8] : Command index
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* DATAPRNT[5] : Data Present Select
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* ENCMDIDX[4] : Command Index Check Enable
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* ENCMDCRC[3] : Command CRC Check Enable
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* RSPTYP[1:0]
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* 00 = No Response
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* 01 = Length 136
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* 10 = Length 48
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* 11 = Length 48 Check busy after response
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*/
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/* Delay added before checking the status of frq change
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* retry not supported by mmc.c(core file)
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*/
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if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
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udelay(50000); /* wait 50 ms */
|
|
if (!(cmd->resp_type & MMC_RSP_PRESENT))
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flags = 0;
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else if (cmd->resp_type & MMC_RSP_136)
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flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
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else if (cmd->resp_type & MMC_RSP_BUSY)
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flags = RSP_TYPE_LGHT48B;
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else
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flags = RSP_TYPE_LGHT48;
|
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/* enable default flags */
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flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
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MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE);
|
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if (cmd->resp_type & MMC_RSP_CRC)
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flags |= CCCE_CHECK;
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if (cmd->resp_type & MMC_RSP_OPCODE)
|
flags |= CICE_CHECK;
|
|
if (data) {
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if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
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(cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
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flags |= (MSBS_MULTIBLK | BCE_ENABLE);
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data->blocksize = 512;
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writel(data->blocksize | (data->blocks << 16),
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&mmc_base->blk);
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} else
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writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
|
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if (data->flags & MMC_DATA_READ)
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flags |= (DP_DATA | DDIR_READ);
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else
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flags |= (DP_DATA | DDIR_WRITE);
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}
|
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writel(cmd->cmdarg, &mmc_base->arg);
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udelay(20); /* To fix "No status update" error on eMMC */
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writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
|
|
start = get_timer(0);
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do {
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mmc_stat = readl(&mmc_base->stat);
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if (get_timer(0) - start > MAX_RETRY_MS) {
|
printf("%s : timeout: No status update\n", __func__);
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return -ETIMEDOUT;
|
}
|
} while (!mmc_stat);
|
|
if ((mmc_stat & IE_CTO) != 0) {
|
mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
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return -ETIMEDOUT;
|
} else if ((mmc_stat & ERRI_MASK) != 0)
|
return -1;
|
|
if (mmc_stat & CC_MASK) {
|
writel(CC_MASK, &mmc_base->stat);
|
if (cmd->resp_type & MMC_RSP_PRESENT) {
|
if (cmd->resp_type & MMC_RSP_136) {
|
/* response type 2 */
|
cmd->response[3] = readl(&mmc_base->rsp10);
|
cmd->response[2] = readl(&mmc_base->rsp32);
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cmd->response[1] = readl(&mmc_base->rsp54);
|
cmd->response[0] = readl(&mmc_base->rsp76);
|
} else
|
/* response types 1, 1b, 3, 4, 5, 6 */
|
cmd->response[0] = readl(&mmc_base->rsp10);
|
}
|
}
|
|
if (data && (data->flags & MMC_DATA_READ)) {
|
mmc_read_data(mmc_base, data->dest,
|
data->blocksize * data->blocks);
|
} else if (data && (data->flags & MMC_DATA_WRITE)) {
|
mmc_write_data(mmc_base, data->src,
|
data->blocksize * data->blocks);
|
}
|
return 0;
|
}
|
|
static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
|
{
|
unsigned int *output_buf = (unsigned int *)buf;
|
unsigned int mmc_stat;
|
unsigned int count;
|
|
/*
|
* Start Polled Read
|
*/
|
count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
|
count /= 4;
|
|
while (size) {
|
ulong start = get_timer(0);
|
do {
|
mmc_stat = readl(&mmc_base->stat);
|
if (get_timer(0) - start > MAX_RETRY_MS) {
|
printf("%s: timedout waiting for status!\n",
|
__func__);
|
return -ETIMEDOUT;
|
}
|
} while (mmc_stat == 0);
|
|
if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
|
mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
|
|
if ((mmc_stat & ERRI_MASK) != 0)
|
return 1;
|
|
if (mmc_stat & BRR_MASK) {
|
unsigned int k;
|
|
writel(readl(&mmc_base->stat) | BRR_MASK,
|
&mmc_base->stat);
|
for (k = 0; k < count; k++) {
|
*output_buf = readl(&mmc_base->data);
|
output_buf++;
|
}
|
size -= (count*4);
|
}
|
|
if (mmc_stat & BWR_MASK)
|
writel(readl(&mmc_base->stat) | BWR_MASK,
|
&mmc_base->stat);
|
|
if (mmc_stat & TC_MASK) {
|
writel(readl(&mmc_base->stat) | TC_MASK,
|
&mmc_base->stat);
|
break;
|
}
|
}
|
return 0;
|
}
|
|
static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
|
unsigned int size)
|
{
|
unsigned int *input_buf = (unsigned int *)buf;
|
unsigned int mmc_stat;
|
unsigned int count;
|
|
/*
|
* Start Polled Write
|
*/
|
count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
|
count /= 4;
|
|
while (size) {
|
ulong start = get_timer(0);
|
do {
|
mmc_stat = readl(&mmc_base->stat);
|
if (get_timer(0) - start > MAX_RETRY_MS) {
|
printf("%s: timedout waiting for status!\n",
|
__func__);
|
return -ETIMEDOUT;
|
}
|
} while (mmc_stat == 0);
|
|
if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
|
mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
|
|
if ((mmc_stat & ERRI_MASK) != 0)
|
return 1;
|
|
if (mmc_stat & BWR_MASK) {
|
unsigned int k;
|
|
writel(readl(&mmc_base->stat) | BWR_MASK,
|
&mmc_base->stat);
|
for (k = 0; k < count; k++) {
|
writel(*input_buf, &mmc_base->data);
|
input_buf++;
|
}
|
size -= (count*4);
|
}
|
|
if (mmc_stat & BRR_MASK)
|
writel(readl(&mmc_base->stat) | BRR_MASK,
|
&mmc_base->stat);
|
|
if (mmc_stat & TC_MASK) {
|
writel(readl(&mmc_base->stat) | TC_MASK,
|
&mmc_base->stat);
|
break;
|
}
|
}
|
return 0;
|
}
|
|
#if !CONFIG_IS_ENABLED(DM_MMC)
|
static int omap_hsmmc_set_ios(struct mmc *mmc)
|
{
|
struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
|
#else
|
static int omap_hsmmc_set_ios(struct udevice *dev)
|
{
|
struct omap_hsmmc_data *priv = dev_get_priv(dev);
|
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
|
struct mmc *mmc = upriv->mmc;
|
#endif
|
struct hsmmc *mmc_base;
|
unsigned int dsor = 0;
|
ulong start;
|
|
mmc_base = priv->base_addr;
|
/* configue bus width */
|
switch (mmc->bus_width) {
|
case 8:
|
writel(readl(&mmc_base->con) | DTW_8_BITMODE,
|
&mmc_base->con);
|
break;
|
|
case 4:
|
writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
|
&mmc_base->con);
|
writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
|
&mmc_base->hctl);
|
break;
|
|
case 1:
|
default:
|
writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
|
&mmc_base->con);
|
writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
|
&mmc_base->hctl);
|
break;
|
}
|
|
/* configure clock with 96Mhz system clock.
|
*/
|
if (mmc->clock != 0) {
|
dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);
|
if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)
|
dsor++;
|
}
|
|
mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
|
(ICE_STOP | DTO_15THDTO | CEN_DISABLE));
|
|
mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
|
(dsor << CLKD_OFFSET) | ICE_OSCILLATE);
|
|
start = get_timer(0);
|
while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
|
if (get_timer(0) - start > MAX_RETRY_MS) {
|
printf("%s: timedout waiting for ics!\n", __func__);
|
return -ETIMEDOUT;
|
}
|
}
|
writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
|
|
return 0;
|
}
|
|
#ifdef OMAP_HSMMC_USE_GPIO
|
#if CONFIG_IS_ENABLED(DM_MMC)
|
static int omap_hsmmc_getcd(struct udevice *dev)
|
{
|
struct omap_hsmmc_data *priv = dev_get_priv(dev);
|
int value;
|
|
value = dm_gpio_get_value(&priv->cd_gpio);
|
/* if no CD return as 1 */
|
if (value < 0)
|
return 1;
|
|
if (priv->cd_inverted)
|
return !value;
|
return value;
|
}
|
|
static int omap_hsmmc_getwp(struct udevice *dev)
|
{
|
struct omap_hsmmc_data *priv = dev_get_priv(dev);
|
int value;
|
|
value = dm_gpio_get_value(&priv->wp_gpio);
|
/* if no WP return as 0 */
|
if (value < 0)
|
return 0;
|
return value;
|
}
|
#else
|
static int omap_hsmmc_getcd(struct mmc *mmc)
|
{
|
struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
|
int cd_gpio;
|
|
/* if no CD return as 1 */
|
cd_gpio = priv->cd_gpio;
|
if (cd_gpio < 0)
|
return 1;
|
|
/* NOTE: assumes card detect signal is active-low */
|
return !gpio_get_value(cd_gpio);
|
}
|
|
static int omap_hsmmc_getwp(struct mmc *mmc)
|
{
|
struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
|
int wp_gpio;
|
|
/* if no WP return as 0 */
|
wp_gpio = priv->wp_gpio;
|
if (wp_gpio < 0)
|
return 0;
|
|
/* NOTE: assumes write protect signal is active-high */
|
return gpio_get_value(wp_gpio);
|
}
|
#endif
|
#endif
|
|
#if CONFIG_IS_ENABLED(DM_MMC)
|
static const struct dm_mmc_ops omap_hsmmc_ops = {
|
.send_cmd = omap_hsmmc_send_cmd,
|
.set_ios = omap_hsmmc_set_ios,
|
#ifdef OMAP_HSMMC_USE_GPIO
|
.get_cd = omap_hsmmc_getcd,
|
.get_wp = omap_hsmmc_getwp,
|
#endif
|
};
|
#else
|
static const struct mmc_ops omap_hsmmc_ops = {
|
.send_cmd = omap_hsmmc_send_cmd,
|
.set_ios = omap_hsmmc_set_ios,
|
.init = omap_hsmmc_init_setup,
|
#ifdef OMAP_HSMMC_USE_GPIO
|
.getcd = omap_hsmmc_getcd,
|
.getwp = omap_hsmmc_getwp,
|
#endif
|
};
|
#endif
|
|
#if !CONFIG_IS_ENABLED(DM_MMC)
|
int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
|
int wp_gpio)
|
{
|
struct mmc *mmc;
|
struct omap_hsmmc_data *priv;
|
struct mmc_config *cfg;
|
uint host_caps_val;
|
|
priv = malloc(sizeof(*priv));
|
if (priv == NULL)
|
return -1;
|
|
host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
|
|
switch (dev_index) {
|
case 0:
|
priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
|
break;
|
#ifdef OMAP_HSMMC2_BASE
|
case 1:
|
priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
|
#if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
|
defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
|
defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
|
defined(CONFIG_HSMMC2_8BIT)
|
/* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
|
host_caps_val |= MMC_MODE_8BIT;
|
#endif
|
break;
|
#endif
|
#ifdef OMAP_HSMMC3_BASE
|
case 2:
|
priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
|
#if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
|
/* Enable 8-bit interface for eMMC on DRA7XX */
|
host_caps_val |= MMC_MODE_8BIT;
|
#endif
|
break;
|
#endif
|
default:
|
priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
|
return 1;
|
}
|
#ifdef OMAP_HSMMC_USE_GPIO
|
/* on error gpio values are set to -1, which is what we want */
|
priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
|
priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
|
#endif
|
|
cfg = &priv->cfg;
|
|
cfg->name = "OMAP SD/MMC";
|
cfg->ops = &omap_hsmmc_ops;
|
|
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
|
cfg->host_caps = host_caps_val & ~host_caps_mask;
|
|
cfg->f_min = 400000;
|
|
if (f_max != 0)
|
cfg->f_max = f_max;
|
else {
|
if (cfg->host_caps & MMC_MODE_HS) {
|
if (cfg->host_caps & MMC_MODE_HS_52MHz)
|
cfg->f_max = 52000000;
|
else
|
cfg->f_max = 26000000;
|
} else
|
cfg->f_max = 20000000;
|
}
|
|
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
|
|
#if defined(CONFIG_OMAP34XX)
|
/*
|
* Silicon revs 2.1 and older do not support multiblock transfers.
|
*/
|
if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
|
cfg->b_max = 1;
|
#endif
|
mmc = mmc_create(cfg, priv);
|
if (mmc == NULL)
|
return -1;
|
|
return 0;
|
}
|
#else
|
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
|
static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
|
{
|
struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
|
struct mmc_config *cfg = &plat->cfg;
|
struct omap2_mmc_platform_config *data =
|
(struct omap2_mmc_platform_config *)dev_get_driver_data(dev);
|
const void *fdt = gd->fdt_blob;
|
int node = dev_of_offset(dev);
|
int val;
|
|
plat->base_addr = map_physmem(devfdt_get_addr(dev),
|
sizeof(struct hsmmc *),
|
MAP_NOCACHE) + data->reg_offset;
|
|
cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
|
val = fdtdec_get_int(fdt, node, "bus-width", -1);
|
if (val < 0) {
|
printf("error: bus-width property missing\n");
|
return -ENOENT;
|
}
|
|
switch (val) {
|
case 0x8:
|
cfg->host_caps |= MMC_MODE_8BIT;
|
case 0x4:
|
cfg->host_caps |= MMC_MODE_4BIT;
|
break;
|
default:
|
printf("error: invalid bus-width property\n");
|
return -ENOENT;
|
}
|
|
cfg->f_min = 400000;
|
cfg->f_max = fdtdec_get_int(fdt, node, "max-frequency", 52000000);
|
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
|
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
|
|
#ifdef OMAP_HSMMC_USE_GPIO
|
plat->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted");
|
#endif
|
|
return 0;
|
}
|
#endif
|
|
#ifdef CONFIG_BLK
|
|
static int omap_hsmmc_bind(struct udevice *dev)
|
{
|
struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
|
|
return mmc_bind(dev, &plat->mmc, &plat->cfg);
|
}
|
#endif
|
static int omap_hsmmc_probe(struct udevice *dev)
|
{
|
struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
|
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
|
struct omap_hsmmc_data *priv = dev_get_priv(dev);
|
struct mmc_config *cfg = &plat->cfg;
|
struct mmc *mmc;
|
|
cfg->name = "OMAP SD/MMC";
|
priv->base_addr = plat->base_addr;
|
#ifdef OMAP_HSMMC_USE_GPIO
|
priv->cd_inverted = plat->cd_inverted;
|
#endif
|
|
#ifdef CONFIG_BLK
|
mmc = &plat->mmc;
|
#else
|
mmc = mmc_create(cfg, priv);
|
if (mmc == NULL)
|
return -1;
|
#endif
|
|
#if defined(OMAP_HSMMC_USE_GPIO) && CONFIG_IS_ENABLED(OF_CONTROL)
|
gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
|
gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
|
#endif
|
|
mmc->dev = dev;
|
upriv->mmc = mmc;
|
|
return omap_hsmmc_init_setup(mmc);
|
}
|
|
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
|
static const struct omap2_mmc_platform_config omap3_mmc_pdata = {
|
.reg_offset = 0,
|
};
|
|
static const struct omap2_mmc_platform_config am33xx_mmc_pdata = {
|
.reg_offset = 0x100,
|
};
|
|
static const struct omap2_mmc_platform_config omap4_mmc_pdata = {
|
.reg_offset = 0x100,
|
};
|
|
static const struct udevice_id omap_hsmmc_ids[] = {
|
{
|
.compatible = "ti,omap3-hsmmc",
|
.data = (ulong)&omap3_mmc_pdata
|
},
|
{
|
.compatible = "ti,omap4-hsmmc",
|
.data = (ulong)&omap4_mmc_pdata
|
},
|
{
|
.compatible = "ti,am33xx-hsmmc",
|
.data = (ulong)&am33xx_mmc_pdata
|
},
|
{ }
|
};
|
#endif
|
|
U_BOOT_DRIVER(omap_hsmmc) = {
|
.name = "omap_hsmmc",
|
.id = UCLASS_MMC,
|
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
|
.of_match = omap_hsmmc_ids,
|
.ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata,
|
.platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat),
|
#endif
|
#ifdef CONFIG_BLK
|
.bind = omap_hsmmc_bind,
|
#endif
|
.ops = &omap_hsmmc_ops,
|
.probe = omap_hsmmc_probe,
|
.priv_auto_alloc_size = sizeof(struct omap_hsmmc_data),
|
.flags = DM_FLAG_PRE_RELOC,
|
};
|
#endif
|
