/*
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* This is a driver for the SDHC controller found in Freescale MX2/MX3
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* SoCs. It is basically the same hardware as found on MX1 (imxmmc.c).
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* Unlike the hardware found on MX1, this hardware just works and does
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* not need all the quirks found in imxmmc.c, hence the seperate driver.
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*
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* Copyright (C) 2009 Ilya Yanok, <yanok@emcraft.com>
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* Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
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* Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
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*
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* derived from pxamci.c by Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <config.h>
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#include <common.h>
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#include <command.h>
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#include <mmc.h>
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#include <part.h>
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#include <malloc.h>
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#include <mmc.h>
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#include <linux/errno.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#define DRIVER_NAME "mxc-mmc"
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struct mxcmci_regs {
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u32 str_stp_clk;
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u32 status;
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u32 clk_rate;
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u32 cmd_dat_cont;
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u32 res_to;
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u32 read_to;
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u32 blk_len;
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u32 nob;
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u32 rev_no;
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u32 int_cntr;
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u32 cmd;
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u32 arg;
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u32 pad;
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u32 res_fifo;
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u32 buffer_access;
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};
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#define STR_STP_CLK_RESET (1 << 3)
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#define STR_STP_CLK_START_CLK (1 << 1)
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#define STR_STP_CLK_STOP_CLK (1 << 0)
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#define STATUS_CARD_INSERTION (1 << 31)
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#define STATUS_CARD_REMOVAL (1 << 30)
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#define STATUS_YBUF_EMPTY (1 << 29)
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#define STATUS_XBUF_EMPTY (1 << 28)
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#define STATUS_YBUF_FULL (1 << 27)
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#define STATUS_XBUF_FULL (1 << 26)
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#define STATUS_BUF_UND_RUN (1 << 25)
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#define STATUS_BUF_OVFL (1 << 24)
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#define STATUS_SDIO_INT_ACTIVE (1 << 14)
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#define STATUS_END_CMD_RESP (1 << 13)
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#define STATUS_WRITE_OP_DONE (1 << 12)
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#define STATUS_DATA_TRANS_DONE (1 << 11)
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#define STATUS_READ_OP_DONE (1 << 11)
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#define STATUS_WR_CRC_ERROR_CODE_MASK (3 << 10)
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#define STATUS_CARD_BUS_CLK_RUN (1 << 8)
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#define STATUS_BUF_READ_RDY (1 << 7)
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#define STATUS_BUF_WRITE_RDY (1 << 6)
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#define STATUS_RESP_CRC_ERR (1 << 5)
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#define STATUS_CRC_READ_ERR (1 << 3)
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#define STATUS_CRC_WRITE_ERR (1 << 2)
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#define STATUS_TIME_OUT_RESP (1 << 1)
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#define STATUS_TIME_OUT_READ (1 << 0)
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#define STATUS_ERR_MASK 0x2f
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#define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1 << 12)
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#define CMD_DAT_CONT_STOP_READWAIT (1 << 11)
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#define CMD_DAT_CONT_START_READWAIT (1 << 10)
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#define CMD_DAT_CONT_BUS_WIDTH_4 (2 << 8)
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#define CMD_DAT_CONT_INIT (1 << 7)
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#define CMD_DAT_CONT_WRITE (1 << 4)
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#define CMD_DAT_CONT_DATA_ENABLE (1 << 3)
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#define CMD_DAT_CONT_RESPONSE_48BIT_CRC (1 << 0)
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#define CMD_DAT_CONT_RESPONSE_136BIT (2 << 0)
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#define CMD_DAT_CONT_RESPONSE_48BIT (3 << 0)
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#define INT_SDIO_INT_WKP_EN (1 << 18)
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#define INT_CARD_INSERTION_WKP_EN (1 << 17)
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#define INT_CARD_REMOVAL_WKP_EN (1 << 16)
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#define INT_CARD_INSERTION_EN (1 << 15)
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#define INT_CARD_REMOVAL_EN (1 << 14)
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#define INT_SDIO_IRQ_EN (1 << 13)
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#define INT_DAT0_EN (1 << 12)
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#define INT_BUF_READ_EN (1 << 4)
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#define INT_BUF_WRITE_EN (1 << 3)
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#define INT_END_CMD_RES_EN (1 << 2)
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#define INT_WRITE_OP_DONE_EN (1 << 1)
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#define INT_READ_OP_EN (1 << 0)
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struct mxcmci_host {
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struct mmc *mmc;
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struct mxcmci_regs *base;
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int irq;
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int detect_irq;
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int dma;
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int do_dma;
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unsigned int power_mode;
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struct mmc_cmd *cmd;
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struct mmc_data *data;
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unsigned int dma_nents;
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unsigned int datasize;
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unsigned int dma_dir;
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u16 rev_no;
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unsigned int cmdat;
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int clock;
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};
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static struct mxcmci_host mxcmci_host;
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/* maintainer note: do we really want to have a global host pointer? */
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static struct mxcmci_host *host = &mxcmci_host;
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static inline int mxcmci_use_dma(struct mxcmci_host *host)
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{
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return host->do_dma;
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}
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static void mxcmci_softreset(struct mxcmci_host *host)
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{
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int i;
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/* reset sequence */
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writel(STR_STP_CLK_RESET, &host->base->str_stp_clk);
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writel(STR_STP_CLK_RESET | STR_STP_CLK_START_CLK,
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&host->base->str_stp_clk);
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for (i = 0; i < 8; i++)
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writel(STR_STP_CLK_START_CLK, &host->base->str_stp_clk);
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writel(0xff, &host->base->res_to);
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}
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static void mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data)
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{
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unsigned int nob = data->blocks;
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unsigned int blksz = data->blocksize;
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unsigned int datasize = nob * blksz;
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host->data = data;
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writel(nob, &host->base->nob);
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writel(blksz, &host->base->blk_len);
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host->datasize = datasize;
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}
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static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_cmd *cmd,
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unsigned int cmdat)
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{
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if (host->cmd != NULL)
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printf("mxcmci: error!\n");
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host->cmd = cmd;
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switch (cmd->resp_type) {
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case MMC_RSP_R1: /* short CRC, OPCODE */
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case MMC_RSP_R1b:/* short CRC, OPCODE, BUSY */
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cmdat |= CMD_DAT_CONT_RESPONSE_48BIT_CRC;
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break;
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case MMC_RSP_R2: /* long 136 bit + CRC */
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cmdat |= CMD_DAT_CONT_RESPONSE_136BIT;
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break;
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case MMC_RSP_R3: /* short */
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cmdat |= CMD_DAT_CONT_RESPONSE_48BIT;
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break;
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case MMC_RSP_NONE:
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break;
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default:
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printf("mxcmci: unhandled response type 0x%x\n",
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cmd->resp_type);
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return -EINVAL;
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}
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writel(cmd->cmdidx, &host->base->cmd);
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writel(cmd->cmdarg, &host->base->arg);
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writel(cmdat, &host->base->cmd_dat_cont);
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return 0;
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}
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static void mxcmci_finish_request(struct mxcmci_host *host,
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struct mmc_cmd *cmd, struct mmc_data *data)
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{
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host->cmd = NULL;
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host->data = NULL;
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}
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static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat)
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{
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int data_error = 0;
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if (stat & STATUS_ERR_MASK) {
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printf("request failed. status: 0x%08x\n",
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stat);
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if (stat & STATUS_CRC_READ_ERR) {
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data_error = -EILSEQ;
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} else if (stat & STATUS_CRC_WRITE_ERR) {
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u32 err_code = (stat >> 9) & 0x3;
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if (err_code == 2) /* No CRC response */
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data_error = -ETIMEDOUT;
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else
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data_error = -EILSEQ;
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} else if (stat & STATUS_TIME_OUT_READ) {
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data_error = -ETIMEDOUT;
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} else {
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data_error = -EIO;
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}
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}
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host->data = NULL;
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return data_error;
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}
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static int mxcmci_read_response(struct mxcmci_host *host, unsigned int stat)
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{
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struct mmc_cmd *cmd = host->cmd;
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int i;
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u32 a, b, c;
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u32 *resp = (u32 *)cmd->response;
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if (!cmd)
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return 0;
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if (stat & STATUS_TIME_OUT_RESP) {
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printf("CMD TIMEOUT\n");
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return -ETIMEDOUT;
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} else if (stat & STATUS_RESP_CRC_ERR && cmd->resp_type & MMC_RSP_CRC) {
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printf("cmd crc error\n");
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return -EILSEQ;
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}
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if (cmd->resp_type & MMC_RSP_PRESENT) {
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if (cmd->resp_type & MMC_RSP_136) {
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for (i = 0; i < 4; i++) {
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a = readl(&host->base->res_fifo) & 0xFFFF;
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b = readl(&host->base->res_fifo) & 0xFFFF;
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resp[i] = a << 16 | b;
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}
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} else {
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a = readl(&host->base->res_fifo) & 0xFFFF;
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b = readl(&host->base->res_fifo) & 0xFFFF;
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c = readl(&host->base->res_fifo) & 0xFFFF;
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resp[0] = a << 24 | b << 8 | c >> 8;
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}
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}
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return 0;
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}
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static int mxcmci_poll_status(struct mxcmci_host *host, u32 mask)
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{
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u32 stat;
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unsigned long timeout = get_ticks() + CONFIG_SYS_HZ;
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do {
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stat = readl(&host->base->status);
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if (stat & STATUS_ERR_MASK)
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return stat;
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if (timeout < get_ticks())
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return STATUS_TIME_OUT_READ;
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if (stat & mask)
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return 0;
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} while (1);
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}
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static int mxcmci_pull(struct mxcmci_host *host, void *_buf, int bytes)
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{
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unsigned int stat;
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u32 *buf = _buf;
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while (bytes > 3) {
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stat = mxcmci_poll_status(host,
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STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
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if (stat)
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return stat;
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*buf++ = readl(&host->base->buffer_access);
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bytes -= 4;
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}
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if (bytes) {
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u8 *b = (u8 *)buf;
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u32 tmp;
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stat = mxcmci_poll_status(host,
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STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
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if (stat)
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return stat;
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tmp = readl(&host->base->buffer_access);
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memcpy(b, &tmp, bytes);
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}
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return 0;
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}
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static int mxcmci_push(struct mxcmci_host *host, const void *_buf, int bytes)
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{
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unsigned int stat;
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const u32 *buf = _buf;
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while (bytes > 3) {
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stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
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if (stat)
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return stat;
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writel(*buf++, &host->base->buffer_access);
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bytes -= 4;
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}
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if (bytes) {
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const u8 *b = (u8 *)buf;
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u32 tmp;
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stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
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if (stat)
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return stat;
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memcpy(&tmp, b, bytes);
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writel(tmp, &host->base->buffer_access);
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}
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stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
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if (stat)
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return stat;
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return 0;
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}
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static int mxcmci_transfer_data(struct mxcmci_host *host)
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{
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struct mmc_data *data = host->data;
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int stat;
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unsigned long length;
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length = data->blocks * data->blocksize;
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host->datasize = 0;
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if (data->flags & MMC_DATA_READ) {
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stat = mxcmci_pull(host, data->dest, length);
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if (stat)
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return stat;
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host->datasize += length;
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} else {
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stat = mxcmci_push(host, (const void *)(data->src), length);
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if (stat)
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return stat;
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host->datasize += length;
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stat = mxcmci_poll_status(host, STATUS_WRITE_OP_DONE);
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if (stat)
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return stat;
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}
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return 0;
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}
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static int mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat)
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{
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int datastat;
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int ret;
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ret = mxcmci_read_response(host, stat);
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if (ret) {
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mxcmci_finish_request(host, host->cmd, host->data);
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return ret;
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}
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if (!host->data) {
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mxcmci_finish_request(host, host->cmd, host->data);
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return 0;
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}
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datastat = mxcmci_transfer_data(host);
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ret = mxcmci_finish_data(host, datastat);
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mxcmci_finish_request(host, host->cmd, host->data);
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return ret;
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}
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static int mxcmci_request(struct mmc *mmc, struct mmc_cmd *cmd,
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struct mmc_data *data)
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{
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struct mxcmci_host *host = mmc->priv;
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unsigned int cmdat = host->cmdat;
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u32 stat;
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int ret;
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host->cmdat &= ~CMD_DAT_CONT_INIT;
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if (data) {
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mxcmci_setup_data(host, data);
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cmdat |= CMD_DAT_CONT_DATA_ENABLE;
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if (data->flags & MMC_DATA_WRITE)
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cmdat |= CMD_DAT_CONT_WRITE;
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}
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if ((ret = mxcmci_start_cmd(host, cmd, cmdat))) {
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mxcmci_finish_request(host, cmd, data);
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return ret;
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}
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do {
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stat = readl(&host->base->status);
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writel(stat, &host->base->status);
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} while (!(stat & STATUS_END_CMD_RESP));
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return mxcmci_cmd_done(host, stat);
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}
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static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios)
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{
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unsigned int divider;
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int prescaler = 0;
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unsigned long clk_in = mxc_get_clock(MXC_ESDHC_CLK);
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while (prescaler <= 0x800) {
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for (divider = 1; divider <= 0xF; divider++) {
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int x;
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x = (clk_in / (divider + 1));
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if (prescaler)
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x /= (prescaler * 2);
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if (x <= clk_ios)
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break;
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}
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if (divider < 0x10)
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break;
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if (prescaler == 0)
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prescaler = 1;
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else
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prescaler <<= 1;
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}
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writel((prescaler << 4) | divider, &host->base->clk_rate);
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}
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static int mxcmci_set_ios(struct mmc *mmc)
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{
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struct mxcmci_host *host = mmc->priv;
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if (mmc->bus_width == 4)
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host->cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
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else
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host->cmdat &= ~CMD_DAT_CONT_BUS_WIDTH_4;
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if (mmc->clock) {
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mxcmci_set_clk_rate(host, mmc->clock);
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writel(STR_STP_CLK_START_CLK, &host->base->str_stp_clk);
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} else {
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writel(STR_STP_CLK_STOP_CLK, &host->base->str_stp_clk);
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}
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host->clock = mmc->clock;
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return 0;
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}
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static int mxcmci_init(struct mmc *mmc)
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{
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struct mxcmci_host *host = mmc->priv;
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mxcmci_softreset(host);
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host->rev_no = readl(&host->base->rev_no);
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if (host->rev_no != 0x400) {
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printf("wrong rev.no. 0x%08x. aborting.\n",
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host->rev_no);
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return -ENODEV;
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}
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/* recommended in data sheet */
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writel(0x2db4, &host->base->read_to);
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writel(0, &host->base->int_cntr);
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return 0;
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}
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static const struct mmc_ops mxcmci_ops = {
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.send_cmd = mxcmci_request,
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.set_ios = mxcmci_set_ios,
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.init = mxcmci_init,
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};
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static struct mmc_config mxcmci_cfg = {
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.name = "MXC MCI",
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.ops = &mxcmci_ops,
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.host_caps = MMC_MODE_4BIT,
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.voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
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.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
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};
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static int mxcmci_initialize(bd_t *bis)
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{
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host->base = (struct mxcmci_regs *)CONFIG_MXC_MCI_REGS_BASE;
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mxcmci_cfg.f_min = mxc_get_clock(MXC_ESDHC_CLK) >> 7;
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mxcmci_cfg.f_max = mxc_get_clock(MXC_ESDHC_CLK) >> 1;
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host->mmc = mmc_create(&mxcmci_cfg, host);
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if (host->mmc == NULL)
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return -1;
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return 0;
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}
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int mxc_mmc_init(bd_t *bis)
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{
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return mxcmci_initialize(bis);
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}
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