/*
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* generic mmc spi driver
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*
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* Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
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* Licensed under the GPL-2 or later.
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*/
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#include <common.h>
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#include <errno.h>
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#include <malloc.h>
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#include <part.h>
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#include <mmc.h>
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#include <spi.h>
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#include <crc.h>
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#include <linux/crc7.h>
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#include <asm/byteorder.h>
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/* MMC/SD in SPI mode reports R1 status always */
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#define R1_SPI_IDLE (1 << 0)
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#define R1_SPI_ERASE_RESET (1 << 1)
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#define R1_SPI_ILLEGAL_COMMAND (1 << 2)
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#define R1_SPI_COM_CRC (1 << 3)
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#define R1_SPI_ERASE_SEQ (1 << 4)
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#define R1_SPI_ADDRESS (1 << 5)
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#define R1_SPI_PARAMETER (1 << 6)
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/* R1 bit 7 is always zero, reuse this bit for error */
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#define R1_SPI_ERROR (1 << 7)
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/* Response tokens used to ack each block written: */
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#define SPI_MMC_RESPONSE_CODE(x) ((x) & 0x1f)
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#define SPI_RESPONSE_ACCEPTED ((2 << 1)|1)
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#define SPI_RESPONSE_CRC_ERR ((5 << 1)|1)
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#define SPI_RESPONSE_WRITE_ERR ((6 << 1)|1)
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/* Read and write blocks start with these tokens and end with crc;
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* on error, read tokens act like a subset of R2_SPI_* values.
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*/
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#define SPI_TOKEN_SINGLE 0xfe /* single block r/w, multiblock read */
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#define SPI_TOKEN_MULTI_WRITE 0xfc /* multiblock write */
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#define SPI_TOKEN_STOP_TRAN 0xfd /* terminate multiblock write */
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/* MMC SPI commands start with a start bit "0" and a transmit bit "1" */
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#define MMC_SPI_CMD(x) (0x40 | (x & 0x3f))
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/* bus capability */
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#define MMC_SPI_VOLTAGE (MMC_VDD_32_33 | MMC_VDD_33_34)
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#define MMC_SPI_MIN_CLOCK 400000 /* 400KHz to meet MMC spec */
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/* timeout value */
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#define CTOUT 8
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#define RTOUT 3000000 /* 1 sec */
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#define WTOUT 3000000 /* 1 sec */
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static uint mmc_spi_sendcmd(struct mmc *mmc, ushort cmdidx, u32 cmdarg)
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{
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struct spi_slave *spi = mmc->priv;
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u8 cmdo[7];
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u8 r1;
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int i;
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cmdo[0] = 0xff;
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cmdo[1] = MMC_SPI_CMD(cmdidx);
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cmdo[2] = cmdarg >> 24;
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cmdo[3] = cmdarg >> 16;
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cmdo[4] = cmdarg >> 8;
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cmdo[5] = cmdarg;
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cmdo[6] = (crc7(0, &cmdo[1], 5) << 1) | 0x01;
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spi_xfer(spi, sizeof(cmdo) * 8, cmdo, NULL, 0);
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for (i = 0; i < CTOUT; i++) {
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spi_xfer(spi, 1 * 8, NULL, &r1, 0);
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if (i && (r1 & 0x80) == 0) /* r1 response */
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break;
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}
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debug("%s:cmd%d resp%d %x\n", __func__, cmdidx, i, r1);
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return r1;
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}
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static uint mmc_spi_readdata(struct mmc *mmc, void *xbuf,
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u32 bcnt, u32 bsize)
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{
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struct spi_slave *spi = mmc->priv;
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u8 *buf = xbuf;
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u8 r1;
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u16 crc;
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int i;
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while (bcnt--) {
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for (i = 0; i < RTOUT; i++) {
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spi_xfer(spi, 1 * 8, NULL, &r1, 0);
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if (r1 != 0xff) /* data token */
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break;
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}
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debug("%s:tok%d %x\n", __func__, i, r1);
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if (r1 == SPI_TOKEN_SINGLE) {
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spi_xfer(spi, bsize * 8, NULL, buf, 0);
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spi_xfer(spi, 2 * 8, NULL, &crc, 0);
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#ifdef CONFIG_MMC_SPI_CRC_ON
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if (be_to_cpu16(crc16_ccitt(0, buf, bsize)) != crc) {
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debug("%s: CRC error\n", mmc->cfg->name);
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r1 = R1_SPI_COM_CRC;
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break;
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}
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#endif
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r1 = 0;
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} else {
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r1 = R1_SPI_ERROR;
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break;
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}
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buf += bsize;
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}
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return r1;
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}
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static uint mmc_spi_writedata(struct mmc *mmc, const void *xbuf,
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u32 bcnt, u32 bsize, int multi)
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{
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struct spi_slave *spi = mmc->priv;
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const u8 *buf = xbuf;
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u8 r1;
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u16 crc;
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u8 tok[2];
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int i;
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tok[0] = 0xff;
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tok[1] = multi ? SPI_TOKEN_MULTI_WRITE : SPI_TOKEN_SINGLE;
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while (bcnt--) {
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#ifdef CONFIG_MMC_SPI_CRC_ON
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crc = cpu_to_be16(crc16_ccitt(0, (u8 *)buf, bsize));
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#endif
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spi_xfer(spi, 2 * 8, tok, NULL, 0);
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spi_xfer(spi, bsize * 8, buf, NULL, 0);
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spi_xfer(spi, 2 * 8, &crc, NULL, 0);
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for (i = 0; i < CTOUT; i++) {
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spi_xfer(spi, 1 * 8, NULL, &r1, 0);
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if ((r1 & 0x10) == 0) /* response token */
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break;
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}
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debug("%s:tok%d %x\n", __func__, i, r1);
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if (SPI_MMC_RESPONSE_CODE(r1) == SPI_RESPONSE_ACCEPTED) {
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for (i = 0; i < WTOUT; i++) { /* wait busy */
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spi_xfer(spi, 1 * 8, NULL, &r1, 0);
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if (i && r1 == 0xff) {
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r1 = 0;
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break;
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}
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}
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if (i == WTOUT) {
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debug("%s:wtout %x\n", __func__, r1);
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r1 = R1_SPI_ERROR;
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break;
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}
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} else {
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debug("%s: err %x\n", __func__, r1);
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r1 = R1_SPI_COM_CRC;
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break;
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}
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buf += bsize;
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}
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if (multi && bcnt == -1) { /* stop multi write */
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tok[1] = SPI_TOKEN_STOP_TRAN;
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spi_xfer(spi, 2 * 8, tok, NULL, 0);
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for (i = 0; i < WTOUT; i++) { /* wait busy */
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spi_xfer(spi, 1 * 8, NULL, &r1, 0);
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if (i && r1 == 0xff) {
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r1 = 0;
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break;
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}
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}
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if (i == WTOUT) {
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debug("%s:wstop %x\n", __func__, r1);
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r1 = R1_SPI_ERROR;
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}
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}
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return r1;
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}
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static int mmc_spi_request(struct mmc *mmc, struct mmc_cmd *cmd,
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struct mmc_data *data)
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{
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struct spi_slave *spi = mmc->priv;
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u8 r1;
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int i;
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int ret = 0;
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debug("%s:cmd%d %x %x\n", __func__,
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cmd->cmdidx, cmd->resp_type, cmd->cmdarg);
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spi_claim_bus(spi);
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spi_cs_activate(spi);
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r1 = mmc_spi_sendcmd(mmc, cmd->cmdidx, cmd->cmdarg);
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if (r1 == 0xff) { /* no response */
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ret = -ENOMEDIUM;
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goto done;
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} else if (r1 & R1_SPI_COM_CRC) {
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ret = -ECOMM;
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goto done;
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} else if (r1 & ~R1_SPI_IDLE) { /* other errors */
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ret = -ETIMEDOUT;
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goto done;
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} else if (cmd->resp_type == MMC_RSP_R2) {
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r1 = mmc_spi_readdata(mmc, cmd->response, 1, 16);
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for (i = 0; i < 4; i++)
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cmd->response[i] = be32_to_cpu(cmd->response[i]);
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debug("r128 %x %x %x %x\n", cmd->response[0], cmd->response[1],
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cmd->response[2], cmd->response[3]);
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} else if (!data) {
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switch (cmd->cmdidx) {
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case SD_CMD_APP_SEND_OP_COND:
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case MMC_CMD_SEND_OP_COND:
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cmd->response[0] = (r1 & R1_SPI_IDLE) ? 0 : OCR_BUSY;
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break;
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case SD_CMD_SEND_IF_COND:
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case MMC_CMD_SPI_READ_OCR:
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spi_xfer(spi, 4 * 8, NULL, cmd->response, 0);
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cmd->response[0] = be32_to_cpu(cmd->response[0]);
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debug("r32 %x\n", cmd->response[0]);
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break;
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case MMC_CMD_SEND_STATUS:
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spi_xfer(spi, 1 * 8, NULL, cmd->response, 0);
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cmd->response[0] = (cmd->response[0] & 0xff) ?
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MMC_STATUS_ERROR : MMC_STATUS_RDY_FOR_DATA;
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break;
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}
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} else {
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debug("%s:data %x %x %x\n", __func__,
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data->flags, data->blocks, data->blocksize);
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if (data->flags == MMC_DATA_READ)
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r1 = mmc_spi_readdata(mmc, data->dest,
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data->blocks, data->blocksize);
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else if (data->flags == MMC_DATA_WRITE)
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r1 = mmc_spi_writedata(mmc, data->src,
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data->blocks, data->blocksize,
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(cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK));
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if (r1 & R1_SPI_COM_CRC)
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ret = -ECOMM;
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else if (r1) /* other errors */
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ret = -ETIMEDOUT;
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}
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done:
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spi_cs_deactivate(spi);
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spi_release_bus(spi);
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return ret;
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}
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static int mmc_spi_set_ios(struct mmc *mmc)
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{
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struct spi_slave *spi = mmc->priv;
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debug("%s: clock %u\n", __func__, mmc->clock);
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if (mmc->clock)
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spi_set_speed(spi, mmc->clock);
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return 0;
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}
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static int mmc_spi_init_p(struct mmc *mmc)
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{
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struct spi_slave *spi = mmc->priv;
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spi_set_speed(spi, MMC_SPI_MIN_CLOCK);
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spi_claim_bus(spi);
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/* cs deactivated for 100+ clock */
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spi_xfer(spi, 18 * 8, NULL, NULL, 0);
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spi_release_bus(spi);
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return 0;
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}
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static const struct mmc_ops mmc_spi_ops = {
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.send_cmd = mmc_spi_request,
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.set_ios = mmc_spi_set_ios,
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.init = mmc_spi_init_p,
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};
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static struct mmc_config mmc_spi_cfg = {
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.name = "MMC_SPI",
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.ops = &mmc_spi_ops,
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.host_caps = MMC_MODE_SPI,
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.voltages = MMC_SPI_VOLTAGE,
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.f_min = MMC_SPI_MIN_CLOCK,
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.part_type = PART_TYPE_DOS,
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.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
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};
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struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode)
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{
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struct mmc *mmc;
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struct spi_slave *spi;
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spi = spi_setup_slave(bus, cs, speed, mode);
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if (spi == NULL)
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return NULL;
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mmc_spi_cfg.f_max = speed;
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mmc = mmc_create(&mmc_spi_cfg, spi);
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if (mmc == NULL) {
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spi_free_slave(spi);
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return NULL;
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}
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return mmc;
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}
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