// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2018 Cisco Systems, Inc.
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*
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* Author: Thomas Fitzsimmons <fitzsim@fitzsim.org>
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*/
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#include <common.h>
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#include <mach/sdhci.h>
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#include <malloc.h>
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#include <sdhci.h>
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/*
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* The BCMSTB SDHCI has a quirk in that its actual maximum frequency
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* capability is 100 MHz. The divisor that is eventually written to
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* SDHCI_CLOCK_CONTROL is calculated based on what the MMC device
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* reports, and relative to this maximum frequency.
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*
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* This define used to be set to 52000000 (52 MHz), the desired
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* maximum frequency, but that would result in the communication
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* actually running at 100 MHz (seemingly without issue), which is
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* out-of-spec.
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*
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* Now, by setting this to 0 (auto-detect), 100 MHz will be read from
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* the capabilities register, and the resulting divisor will be
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* doubled, meaning that the clock control register will be set to the
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* in-spec 52 MHz value.
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*/
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#define BCMSTB_SDHCI_MAXIMUM_CLOCK_FREQUENCY 0
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/*
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* When the minimum clock frequency is set to 0 (auto-detect), U-Boot
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* sets it to 100 MHz divided by SDHCI_MAX_DIV_SPEC_300, or 48,875 Hz,
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* which results in the controller timing out when trying to
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* communicate with the MMC device. Hard-code this value to 400000
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* (400 kHz) to prevent this.
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*/
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#define BCMSTB_SDHCI_MINIMUM_CLOCK_FREQUENCY 400000
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static char *BCMSTB_SDHCI_NAME = "bcmstb-sdhci";
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/*
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* This driver has only been tested with eMMC devices; SD devices may
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* not work.
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*/
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int bcmstb_sdhci_init(phys_addr_t regbase)
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{
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struct sdhci_host *host = NULL;
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host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
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if (!host) {
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printf("%s: Failed to allocate memory\n", __func__);
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return 1;
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}
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memset(host, 0, sizeof(*host));
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host->name = BCMSTB_SDHCI_NAME;
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host->ioaddr = (void *)regbase;
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host->quirks = 0;
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host->cfg.part_type = PART_TYPE_DOS;
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host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
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return add_sdhci(host,
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BCMSTB_SDHCI_MAXIMUM_CLOCK_FREQUENCY,
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BCMSTB_SDHCI_MINIMUM_CLOCK_FREQUENCY);
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}
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