/*
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* Freescale i.MX28 OCOTP Driver
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*
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* Copyright (C) 2014 Marek Vasut <marex@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Note: The i.MX23/i.MX28 OCOTP block is a predecessor to the OCOTP block
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* used in i.MX6 . While these blocks are very similar at the first
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* glance, by digging deeper, one will notice differences (like the
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* tight dependence on MXS power block, some completely new registers
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* etc.) which would make common driver an ifdef nightmare :-(
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*/
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#include <common.h>
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#include <fuse.h>
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#include <linux/errno.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/sys_proto.h>
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#define MXS_OCOTP_TIMEOUT 100000
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static struct mxs_ocotp_regs *ocotp_regs =
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(struct mxs_ocotp_regs *)MXS_OCOTP_BASE;
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static struct mxs_power_regs *power_regs =
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(struct mxs_power_regs *)MXS_POWER_BASE;
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static struct mxs_clkctrl_regs *clkctrl_regs =
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(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
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static int mxs_ocotp_wait_busy_clear(void)
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{
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uint32_t reg;
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int timeout = MXS_OCOTP_TIMEOUT;
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while (--timeout) {
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reg = readl(&ocotp_regs->hw_ocotp_ctrl);
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if (!(reg & OCOTP_CTRL_BUSY))
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break;
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udelay(10);
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}
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if (!timeout)
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return -EINVAL;
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/* Wait a little as per FSL datasheet's 'write postamble' section. */
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udelay(10);
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return 0;
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}
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static void mxs_ocotp_clear_error(void)
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{
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writel(OCOTP_CTRL_ERROR, &ocotp_regs->hw_ocotp_ctrl_clr);
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}
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static int mxs_ocotp_read_bank_open(bool open)
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{
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int ret = 0;
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if (open) {
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writel(OCOTP_CTRL_RD_BANK_OPEN,
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&ocotp_regs->hw_ocotp_ctrl_set);
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/*
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* Wait before polling the BUSY bit, since the BUSY bit might
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* be asserted only after a few HCLK cycles and if we were to
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* poll immediatelly, we could miss the busy bit.
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*/
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udelay(10);
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ret = mxs_ocotp_wait_busy_clear();
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} else {
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writel(OCOTP_CTRL_RD_BANK_OPEN,
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&ocotp_regs->hw_ocotp_ctrl_clr);
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}
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return ret;
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}
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static void mxs_ocotp_scale_vddio(bool enter, uint32_t *val)
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{
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uint32_t scale_val;
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if (enter) {
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/*
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* Enter the fuse programming VDDIO voltage setup. We start
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* scaling the voltage from it's current value down to 2.8V
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* which is the one and only correct voltage for programming
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* the OCOTP fuses (according to datasheet).
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*/
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scale_val = readl(&power_regs->hw_power_vddioctrl);
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scale_val &= POWER_VDDIOCTRL_TRG_MASK;
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/* Return the original voltage. */
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*val = scale_val;
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/*
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* Start scaling VDDIO down to 0x2, which is 2.8V . Actually,
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* the value 0x0 should be 2.8V, but that's not the case on
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* most designs due to load etc., so we play safe. Undervolt
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* can actually cause incorrect programming of the fuses and
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* or reboots of the board.
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*/
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while (scale_val > 2) {
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clrsetbits_le32(&power_regs->hw_power_vddioctrl,
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POWER_VDDIOCTRL_TRG_MASK, --scale_val);
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udelay(500);
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}
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} else {
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/* Start scaling VDDIO up to original value . */
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for (scale_val = 2; scale_val <= *val; scale_val++) {
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clrsetbits_le32(&power_regs->hw_power_vddioctrl,
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POWER_VDDIOCTRL_TRG_MASK, scale_val);
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udelay(500);
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}
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}
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mdelay(10);
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}
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static int mxs_ocotp_wait_hclk_ready(void)
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{
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uint32_t reg, timeout = MXS_OCOTP_TIMEOUT;
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while (--timeout) {
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reg = readl(&clkctrl_regs->hw_clkctrl_hbus);
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if (!(reg & CLKCTRL_HBUS_ASM_BUSY))
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break;
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}
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if (!timeout)
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return -EINVAL;
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return 0;
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}
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static int mxs_ocotp_scale_hclk(bool enter, uint32_t *val)
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{
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uint32_t scale_val;
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int ret;
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ret = mxs_ocotp_wait_hclk_ready();
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if (ret)
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return ret;
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/* Set CPU bypass */
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writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
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&clkctrl_regs->hw_clkctrl_clkseq_set);
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if (enter) {
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/* Return the original HCLK clock speed. */
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*val = readl(&clkctrl_regs->hw_clkctrl_hbus);
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*val &= CLKCTRL_HBUS_DIV_MASK;
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*val >>= CLKCTRL_HBUS_DIV_OFFSET;
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/* Scale the HCLK to 454/19 = 23.9 MHz . */
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scale_val = (~19) << CLKCTRL_HBUS_DIV_OFFSET;
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scale_val &= CLKCTRL_HBUS_DIV_MASK;
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} else {
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/* Scale the HCLK back to original frequency. */
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scale_val = (~(*val)) << CLKCTRL_HBUS_DIV_OFFSET;
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scale_val &= CLKCTRL_HBUS_DIV_MASK;
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}
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writel(CLKCTRL_HBUS_DIV_MASK,
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&clkctrl_regs->hw_clkctrl_hbus_set);
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writel(scale_val,
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&clkctrl_regs->hw_clkctrl_hbus_clr);
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mdelay(10);
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ret = mxs_ocotp_wait_hclk_ready();
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if (ret)
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return ret;
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/* Disable CPU bypass */
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writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
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&clkctrl_regs->hw_clkctrl_clkseq_clr);
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mdelay(10);
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return 0;
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}
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static int mxs_ocotp_write_fuse(uint32_t addr, uint32_t mask)
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{
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uint32_t hclk_val, vddio_val;
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int ret;
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mxs_ocotp_clear_error();
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/* Make sure the banks are closed for reading. */
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ret = mxs_ocotp_read_bank_open(0);
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if (ret) {
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puts("Failed closing banks for reading!\n");
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return ret;
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}
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ret = mxs_ocotp_scale_hclk(1, &hclk_val);
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if (ret) {
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puts("Failed scaling down the HCLK!\n");
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return ret;
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}
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mxs_ocotp_scale_vddio(1, &vddio_val);
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ret = mxs_ocotp_wait_busy_clear();
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if (ret) {
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puts("Failed waiting for ready state!\n");
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goto fail;
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}
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/* Program the fuse address */
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writel(addr | OCOTP_CTRL_WR_UNLOCK_KEY, &ocotp_regs->hw_ocotp_ctrl);
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/* Program the data. */
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writel(mask, &ocotp_regs->hw_ocotp_data);
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udelay(10);
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ret = mxs_ocotp_wait_busy_clear();
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if (ret) {
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puts("Failed waiting for ready state!\n");
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goto fail;
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}
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/* Check for errors */
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if (readl(&ocotp_regs->hw_ocotp_ctrl) & OCOTP_CTRL_ERROR) {
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puts("Failed writing fuses!\n");
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ret = -EPERM;
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goto fail;
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}
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fail:
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mxs_ocotp_scale_vddio(0, &vddio_val);
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if (mxs_ocotp_scale_hclk(0, &hclk_val))
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puts("Failed scaling up the HCLK!\n");
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return ret;
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}
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static int mxs_ocotp_read_fuse(uint32_t reg, uint32_t *val)
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{
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int ret;
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/* Register offset from CUST0 */
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reg = ((uint32_t)&ocotp_regs->hw_ocotp_cust0) + (reg << 4);
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ret = mxs_ocotp_wait_busy_clear();
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if (ret) {
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puts("Failed waiting for ready state!\n");
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return ret;
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}
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mxs_ocotp_clear_error();
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ret = mxs_ocotp_read_bank_open(1);
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if (ret) {
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puts("Failed opening banks for reading!\n");
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return ret;
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}
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*val = readl(reg);
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ret = mxs_ocotp_read_bank_open(0);
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if (ret) {
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puts("Failed closing banks for reading!\n");
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return ret;
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}
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return ret;
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}
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static int mxs_ocotp_valid(u32 bank, u32 word)
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{
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if (bank > 4)
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return -EINVAL;
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if (word > 7)
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return -EINVAL;
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return 0;
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}
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/*
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* The 'fuse' command API
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*/
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int fuse_read(u32 bank, u32 word, u32 *val)
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{
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int ret;
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ret = mxs_ocotp_valid(bank, word);
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if (ret)
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return ret;
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return mxs_ocotp_read_fuse((bank << 3) | word, val);
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}
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int fuse_prog(u32 bank, u32 word, u32 val)
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{
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int ret;
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ret = mxs_ocotp_valid(bank, word);
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if (ret)
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return ret;
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return mxs_ocotp_write_fuse((bank << 3) | word, val);
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}
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int fuse_sense(u32 bank, u32 word, u32 *val)
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{
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/* We do not support sensing :-( */
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return -EINVAL;
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}
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int fuse_override(u32 bank, u32 word, u32 val)
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{
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/* We do not support overriding :-( */
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return -EINVAL;
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}
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