/*
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* (C) Copyright 2009-2013 ADVANSEE
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* Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
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*
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* Based on the mpc512x iim code:
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* Copyright 2008 Silicon Turnkey Express, Inc.
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* Martha Marx <mmarx@silicontkx.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <fuse.h>
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#include <linux/errno.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
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#include <asm/arch/clock.h>
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#endif
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/* FSL IIM-specific constants */
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#define STAT_BUSY 0x80
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#define STAT_PRGD 0x02
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#define STAT_SNSD 0x01
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#define STATM_PRGD_M 0x02
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#define STATM_SNSD_M 0x01
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#define ERR_PRGE 0x80
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#define ERR_WPE 0x40
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#define ERR_OPE 0x20
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#define ERR_RPE 0x10
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#define ERR_WLRE 0x08
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#define ERR_SNSE 0x04
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#define ERR_PARITYE 0x02
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#define EMASK_PRGE_M 0x80
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#define EMASK_WPE_M 0x40
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#define EMASK_OPE_M 0x20
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#define EMASK_RPE_M 0x10
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#define EMASK_WLRE_M 0x08
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#define EMASK_SNSE_M 0x04
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#define EMASK_PARITYE_M 0x02
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#define FCTL_DPC 0x80
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#define FCTL_PRG_LENGTH_MASK 0x70
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#define FCTL_ESNS_N 0x08
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#define FCTL_ESNS_0 0x04
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#define FCTL_ESNS_1 0x02
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#define FCTL_PRG 0x01
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#define UA_A_BANK_MASK 0x38
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#define UA_A_ROWH_MASK 0x07
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#define LA_A_ROWL_MASK 0xf8
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#define LA_A_BIT_MASK 0x07
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#define PREV_PROD_REV_MASK 0xf8
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#define PREV_PROD_VT_MASK 0x07
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/* Select the correct accessors depending on endianness */
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#if __BYTE_ORDER == __LITTLE_ENDIAN
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#define iim_read32 in_le32
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#define iim_write32 out_le32
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#define iim_clrsetbits32 clrsetbits_le32
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#define iim_clrbits32 clrbits_le32
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#define iim_setbits32 setbits_le32
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#elif __BYTE_ORDER == __BIG_ENDIAN
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#define iim_read32 in_be32
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#define iim_write32 out_be32
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#define iim_clrsetbits32 clrsetbits_be32
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#define iim_clrbits32 clrbits_be32
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#define iim_setbits32 setbits_be32
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#else
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#error Endianess is not defined: please fix to continue
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#endif
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/* IIM control registers */
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struct fsl_iim {
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u32 stat;
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u32 statm;
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u32 err;
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u32 emask;
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u32 fctl;
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u32 ua;
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u32 la;
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u32 sdat;
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u32 prev;
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u32 srev;
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u32 prg_p;
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u32 scs[0x1f5];
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struct {
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u32 word[0x100];
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} bank[8];
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};
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#if !defined(CONFIG_MX51) && !defined(CONFIG_MX53)
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#define enable_efuse_prog_supply(enable)
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#endif
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static int prepare_access(struct fsl_iim **regs, u32 bank, u32 word, int assert,
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const char *caller)
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{
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*regs = (struct fsl_iim *)IIM_BASE_ADDR;
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if (bank >= ARRAY_SIZE((*regs)->bank) ||
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word >= ARRAY_SIZE((*regs)->bank[0].word) ||
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!assert) {
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printf("fsl_iim %s(): Invalid argument\n", caller);
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return -EINVAL;
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}
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return 0;
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}
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static void clear_status(struct fsl_iim *regs)
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{
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iim_setbits32(®s->stat, 0);
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iim_setbits32(®s->err, 0);
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}
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static void finish_access(struct fsl_iim *regs, u32 *stat, u32 *err)
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{
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*stat = iim_read32(®s->stat);
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*err = iim_read32(®s->err);
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clear_status(regs);
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}
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static int prepare_read(struct fsl_iim **regs, u32 bank, u32 word, u32 *val,
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const char *caller)
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{
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int ret;
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ret = prepare_access(regs, bank, word, val != NULL, caller);
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if (ret)
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return ret;
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clear_status(*regs);
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return 0;
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}
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int fuse_read(u32 bank, u32 word, u32 *val)
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{
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struct fsl_iim *regs;
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u32 stat, err;
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int ret;
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ret = prepare_read(®s, bank, word, val, __func__);
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if (ret)
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return ret;
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*val = iim_read32(®s->bank[bank].word[word]);
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finish_access(regs, &stat, &err);
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if (err & ERR_RPE) {
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puts("fsl_iim fuse_read(): Read protect error\n");
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return -EIO;
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}
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return 0;
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}
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static void direct_access(struct fsl_iim *regs, u32 bank, u32 word, u32 bit,
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u32 fctl, u32 *stat, u32 *err)
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{
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iim_write32(®s->ua, bank << 3 | word >> 5);
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iim_write32(®s->la, (word << 3 | bit) & 0xff);
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if (fctl == FCTL_PRG)
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iim_write32(®s->prg_p, 0xaa);
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iim_setbits32(®s->fctl, fctl);
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while (iim_read32(®s->stat) & STAT_BUSY)
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udelay(20);
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finish_access(regs, stat, err);
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}
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int fuse_sense(u32 bank, u32 word, u32 *val)
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{
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struct fsl_iim *regs;
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u32 stat, err;
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int ret;
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ret = prepare_read(®s, bank, word, val, __func__);
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if (ret)
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return ret;
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direct_access(regs, bank, word, 0, FCTL_ESNS_N, &stat, &err);
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if (err & ERR_SNSE) {
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puts("fsl_iim fuse_sense(): Explicit sense cycle error\n");
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return -EIO;
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}
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if (!(stat & STAT_SNSD)) {
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puts("fsl_iim fuse_sense(): Explicit sense cycle did not complete\n");
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return -EIO;
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}
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*val = iim_read32(®s->sdat);
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return 0;
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}
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static int prog_bit(struct fsl_iim *regs, u32 bank, u32 word, u32 bit)
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{
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u32 stat, err;
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clear_status(regs);
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direct_access(regs, bank, word, bit, FCTL_PRG, &stat, &err);
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iim_write32(®s->prg_p, 0x00);
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if (err & ERR_PRGE) {
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puts("fsl_iim fuse_prog(): Program error\n");
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return -EIO;
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}
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if (err & ERR_WPE) {
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puts("fsl_iim fuse_prog(): Write protect error\n");
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return -EIO;
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}
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if (!(stat & STAT_PRGD)) {
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puts("fsl_iim fuse_prog(): Program did not complete\n");
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return -EIO;
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}
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return 0;
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}
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static int prepare_write(struct fsl_iim **regs, u32 bank, u32 word, u32 val,
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const char *caller)
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{
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return prepare_access(regs, bank, word, !(val & ~0xff), caller);
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}
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int fuse_prog(u32 bank, u32 word, u32 val)
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{
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struct fsl_iim *regs;
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u32 bit;
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int ret;
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ret = prepare_write(®s, bank, word, val, __func__);
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if (ret)
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return ret;
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enable_efuse_prog_supply(1);
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for (bit = 0; val; bit++, val >>= 1)
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if (val & 0x01) {
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ret = prog_bit(regs, bank, word, bit);
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if (ret) {
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enable_efuse_prog_supply(0);
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return ret;
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}
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}
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enable_efuse_prog_supply(0);
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return 0;
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}
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int fuse_override(u32 bank, u32 word, u32 val)
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{
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struct fsl_iim *regs;
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u32 stat, err;
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int ret;
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ret = prepare_write(®s, bank, word, val, __func__);
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if (ret)
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return ret;
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clear_status(regs);
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iim_write32(®s->bank[bank].word[word], val);
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finish_access(regs, &stat, &err);
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if (err & ERR_OPE) {
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puts("fsl_iim fuse_override(): Override protect error\n");
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return -EIO;
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}
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return 0;
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}
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