SPI/QSPI Dual flash connection modes:
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=====================================
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This describes how SPI/QSPI flash memories are connected to a given
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controller in a single chip select line.
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Current spi_flash framework supports, single flash memory connected
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to a given controller with single chip select line, but there are some
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hw logics(ex: xilinx zynq qspi) that describes two/dual memories are
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connected with a single chip select line from a controller.
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"dual_flash" from include/spi.h describes these types of connection mode
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Possible connections:
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--------------------
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SF_SINGLE_FLASH:
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- single spi flash memory connected with single chip select line.
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+------------+ CS +---------------+
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| |----------------------->| |
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| Controller | I0[3:0] | Flash memory |
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| SPI/QSPI |<======================>| (SPI/QSPI) |
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| | CLK | |
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| |----------------------->| |
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+------------+ +---------------+
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SF_DUAL_STACKED_FLASH:
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- dual spi/qspi flash memories are connected with a single chipselect
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line and these two memories are operating stacked fasion with shared buses.
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- xilinx zynq qspi controller has implemented this feature [1]
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+------------+ CS +---------------+
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| |---------------------->| |
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| | I0[3:0] | Upper Flash |
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| | +=========>| memory |
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| | | CLK | (SPI/QSPI) |
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| | | +---->| |
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| Controller | CS | | +---------------+
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| SPI/QSPI |------------|----|---->| |
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| | I0[3:0] | | | Lower Flash |
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| |<===========+====|====>| memory |
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| | CLK | | (SPI/QSPI) |
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| |-----------------+---->| |
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+------------+ +---------------+
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- two memory flash devices should has same hw part attributes (like size,
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vendor..etc)
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- Configurations:
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on LQSPI_CFG register, Enable TWO_MEM[BIT:30] on LQSPI_CFG
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Enable U_PAGE[BIT:28] if U_PAGE flag set - upper memory
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Disable U_PAGE[BIT:28] if U_PAGE flag unset - lower memory
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- Operation:
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accessing memories serially like one after another.
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by default, if U_PAGE is unset lower memory should accessible,
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once user wants to access upper memory need to set U_PAGE.
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SPI_FLASH_CONN_DUALPARALLEL:
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- dual spi/qspi flash memories are connected with a single chipselect
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line and these two memories are operating parallel with separate buses.
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- xilinx zynq qspi controller has implemented this feature [1]
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+-------------+ CS +---------------+
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| |---------------------->| |
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| | I0[3:0] | Upper Flash |
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| |<=====================>| memory |
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| | CLK | (SPI/QSPI) |
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| |---------------------->| |
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| Controller | CS +---------------+
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| SPI/QSPI |---------------------->| |
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| | I0[3:0] | Lower Flash |
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| |<=====================>| memory |
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| | CLK | (SPI/QSPI) |
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| |---------------------->| |
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+-------------+ +---------------+
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- two memory flash devices should has same hw part attributes (like size,
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vendor..etc)
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- Configurations:
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Need to enable SEP_BUS[BIT:29],TWO_MEM[BIT:30] on LQSPI_CFG register.
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- Operation:
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Even bits, i.e. bit 0, 2, 4 ., of a data word is located in the lower memory
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and odd bits, i.e. bit 1, 3, 5, ., of a data word is located in the upper memory.
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Note: Technically there is only one CS line from the controller, but
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zynq qspi controller has an internal hw logic to enable additional CS
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when controller is configured for dual memories.
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[1] http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
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--
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Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
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05-01-2014.
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