Overview
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--------
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The LS1021ATWR is a Freescale reference board that hosts the LS1021A SoC.
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LS1021A SoC Overview
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The QorIQ LS1 family, which includes the LS1021A communications processor,
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is built on Layerscape architecture, the industry's first software-aware,
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core-agnostic networking architecture to offer unprecedented efficiency
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and scale.
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A member of the value-performance tier, the QorIQ LS1021A processor provides
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extensive integration and power efficiency for fanless, small form factor
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enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
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running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
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performance of over 6,000, as well as virtualization support, advanced
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security features and the broadest array of high-speed interconnects and
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optimized peripheral features ever offered in a sub-3 W processor.
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The QorIQ LS1021A processor features an integrated LCD controller,
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CAN controller for implementing industrial protocols, DDR3L/4 running
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up to 1600 MHz, integrated security engine and QUICC Engine, and ECC
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protection on both L1 and L2 caches. The LS1021A processor is pin- and
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software-compatible with the QorIQ LS1020A and LS1022A processors.
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The LS1021A SoC includes the following function and features:
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- ARM Cortex-A7 MPCore compliant with ARMv7-A architecture
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- Dual high-preformance ARM Cortex-A7 cores, each core includes:
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- 32 Kbyte L1 Instruction Cache and Data Cache for each core (ECC protection)
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- 512 Kbyte shared coherent L2 Cache (with ECC protection)
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- NEON Co-processor (per core)
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- 40-bit physical addressing
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- Vector floating-point support
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- ARM Core-Link CCI-400 Cache Coherent Interconnect
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- One DDR3L/DDR4 SDRAM memory controller with x8/x16/x32-bit configuration
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supporting speeds up to 1600Mtps
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- ECC and interleaving support
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- VeTSEC Ethernet complex
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- Up to 3x virtualized 10/100/1000 Ethernet controllers
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- MII, RMII, RGMII, and SGMII support
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- QoS, lossless flow control, and IEEE 1588 support
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- 4-lane 6GHz SerDes
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- High speed interconnect (4 SerDes lanes with are muxed for these protocol)
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- Two PCI Express Gen2 controllers running at up to 5 GHz
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- One Serial ATA 3.0 supporting 6 GT/s operation
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- Two SGMII interfaces supporting 1000 Mbps
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- Additional peripheral interfaces
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- One high-speed USB 3.0 controller with integrated PHY and one high-speed
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USB 2.00 controller with ULPI
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- Integrated flash controller (IFC) with 16-bit interface
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- Quad SPI NOR Flash
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- One enhanced Secure digital host controller
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- Display controller unit (DCU) 24-bit RGB (12-bit DDR pin interface)
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- Ten UARTs comprised of two 16550 compliant DUARTs, and six low power
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UARTs
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- Three I2C controllers
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- Eight FlexTimers four supporting PWM and four FlexCAN ports
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- Four GPIO controllers supporting up to 109 general purpose I/O signals
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- Integrated advanced audio block:
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- Four synchronous audio interfaces (SAI)
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- Sony/Philips Digital Interconnect Format (SPDIF)
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- Asynchronous Sample Rate Converter (ASRC)
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- Hardware based crypto offload engine
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- IPSec forwarding at up to 1Gbps
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- QorIQ Trust Architecture, Secure Boot, and ARM TrustZone supported
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- Public key hardware accelerator
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- True Random Number Generator (NIST Certified)
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- Advanced Encryption Standard Accelerators (AESA)
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- Data Encryption Standard Accelerators
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- QUICC Engine ULite block
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- Two universal communication controllers (TDM and HDLC) supporting 64
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multichannels, each running at 64 Kbps
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- Support for 256 channels of HDLC
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- QorIQ TrustArchitecture with Secure Boot, as well as ARM TrustZone supported
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LS1021ATWR board Overview
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-------------------------
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- DDR Controller
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- Supports rates of up to 1600 MHz data-rate
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- Supports one DDR3LP SDRAM.
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- IFC/Local Bus
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- NOR: 128MB 16-bit NOR Flash
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- Ethernet
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- Three on-board RGMII 10/100/1G ethernet ports.
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- CPLD
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- Clocks
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- System and DDR clock (SYSCLK, DDRCLK)
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- SERDES clocks
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- Power Supplies
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- SDHC
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- SDHC/SDXC connector
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- Other IO
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- One Serial port
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- Three I2C ports
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Memory map
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-----------
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The addresses in brackets are physical addresses.
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Start Address End Address Description Size
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0x00_0000_0000 0x00_000F_FFFF Secure Boot ROM 1MB
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0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB
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0x00_1000_0000 0x00_1000_FFFF OCRAM0 64KB
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0x00_1001_0000 0x00_1001_FFFF OCRAM1 64KB
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0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB
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0x00_4000_0000 0x00_5FFF_FFFF QSPI 512MB
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0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB
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0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB
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LS1021a rev1.0 Soc specific Options/Settings
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--------------------------------------------
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If the LS1021a Soc is rev1.0, you need modify the configure file.
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Add the following define in include/configs/ls1021atwr.h:
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#define CONFIG_SKIP_LOWLEVEL_INIT
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