Overview
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--------
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The BSC9132 is a highly integrated device that targets the evolving
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Microcell, Picocell, and Enterprise-Femto base station market subsegments.
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The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850
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core technologies with MAPLE-B2P baseband acceleration processing elements
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to address the need for a high performance, low cost, integrated solution
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that handles all required processing layers without the need for an
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external device except for an RF transceiver or, in a Micro base station
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configuration, a host device that handles the L3/L4 and handover between
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sectors.
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The BSC9132 SoC includes the following function and features:
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- Power Architecture subsystem including two e500 processors with
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512-Kbyte shared L2 cache
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- Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2
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cache
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- 32 Kbyte of shared M3 memory
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- The Multi Accelerator Platform Engine for Pico BaseStation Baseband
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Processing (MAPLE-B2P)
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- Two DDR3/3L memory interfaces with 32-bit data width (40 bits including
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ECC), up to 1333 MHz data rate
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- Dedicated security engine featuring trusted boot
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- Two DMA controllers
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- OCNDMA with four bidirectional channels
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- SysDMA with sixteen bidirectional channels
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- Interfaces
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- Four-lane SerDes PHY
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- PCI Express controller complies with the PEX Specification-Rev 2.0
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- Two Common Public Radio Interface (CPRI) controller lanes
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- High-speed USB 2.0 host and device controller with ULPI interface
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- Enhanced secure digital (SD/MMC) host controller (eSDHC)
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- Antenna interface controller (AIC), supporting four industry
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standard JESD207/four custom ADI RF interfaces
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- ADI lanes support both full duplex FDD support & half duplex TDD
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- Universal Subscriber Identity Module (USIM) interface that
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facilitates communication to SIM cards or Eurochip pre-paid phone
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cards
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- Two DUART, two eSPI, and two I2C controllers
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- Integrated Flash memory controller (IFC)
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- GPIO
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- Sixteen 32-bit timers
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The SC3850 core subsystem consists of the following:
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- 32 KB, 8-way, level 1 instruction cache (L1 ICache)
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- 32 KB, 8-way, level 1 data cache (L1 DCache)
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- 512 KB, 8-way, level 2 unified instruction/data cache (L2 cache/M2 memory)
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- Memory management unit (MMU)
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- Global interrupt controller ( GIC)
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- Debug and profiling unit (DPU)
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- Two 32-bit quad timers
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BSC9132QDS board Overview
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-------------------------
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2Gbyte DDR3 (on board DDR), Dual Ranki
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32Mbyte 16bit NOR flash
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128Mbyte 2K page size NAND Flash
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256 Kbit M24256 I2C EEPROM
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128 Mbit SPI Flash memory
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SD slot
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USB-ULPI
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eTSEC1: Connected to SGMII PHY
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eTSEC2: Connected to SGMII PHY
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PCIe
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CPRI
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SerDes
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I2C RTC
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DUART interface: supports one UARTs up to 115200 bps for console display
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Frequency Combinations Supported
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--------------------------------
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Core MHz/CCB MHz/DDR(MT/s)
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1. CPU0/CPU1/CCB/DDR: 1000MHz/1000MHz/500MHz/800MHz
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(SYSCLK = 100MHz, DDRCLK = 100MHz)
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2. CPU0/CPU1/CCB/DDR: 1200MHz/1200MHz/600MHz/1330MHz
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(SYSCLK = 100MHz, DDRCLK = 133MHz)
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Boot Methods Supported
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-----------------------
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1. NOR Flash
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2. NAND Flash
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3. SD Card
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4. SPI flash
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Default Boot Method
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--------------------
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NOR boot
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Building U-Boot
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--------------
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To build the U-Boot for BSC9132QDS:
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1. NOR Flash
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make BSC9132QDS_NOR_DDRCLK100 : For 100MHZ DDR CLK
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make BSC9132QDS_NOR_DDRCLK133 : For 133MHZ DDR CLK
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2. NAND Flash : It is currently not supported
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3. SPI Flash
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make BSC9132QDS_SPIFLASH_DDRCLK100 : For 100MHZ DDR CLK
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make BSC9132QDS_SPIFLASH_DDRCLK133 : For 133MHZ DDR CLK
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4. SD Card
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make BSC9132QDS_SDCARD_DDRCLK100 : For 100MHZ DDR CLK
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make BSC9132QDS_SDCARD_DDRCLK133 : For 133MHZ DDR CLK
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Memory map
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-----------
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0x0000_0000 0x7FFF_FFFF DDR 2G cacheable
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0x8000_0000 0x8FFF_FFFF NOR Flash 256M
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0x9000_0000 0x9FFF_FFFF PCIe Memory 256M
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0xA000_0000 0xA7FF_FFFF DSP core1 L2 space 128M
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0xB000_0000 0xB0FF_FFFF DSP core0 M2 space 16M
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0xB100_0000 0xB1FF_FFFF DSP core1 M2 space 16M
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0xC000_0000 0xC000_7FFF M3 Memory 32K
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0xC001_0000 0xC001_FFFF PCI Express I/O 64K
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0xC100_0000 0xC13F_FFFF MAPLE-2F 4M
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0xC1F0_0000 0xC1F7_FFFF PA SRAM Region 0 512K
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0xC1F8_0000 0xC1FB_FFFF PA SRAM Region 1 512K
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0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K
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0xFEE0_0000 0xFEE0_0FFF DSP Boot ROM 4K
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0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M
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0xFF70_0000 0xFF7F_FFFF PA CCSR 1M
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0xFF80_0000 0xFFFF_FFFF Boot Page & NAND Buffer 8M
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Flashing Images
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---------------
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To place a new U-Boot image in the NAND flash and then boot
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with that new image temporarily, use this:
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tftp 1000000 u-boot-nand.bin
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nand erase 0 100000
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nand write 1000000 0 100000
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reset
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Using the Device Tree Source File
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---------------------------------
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To create the DTB (Device Tree Binary) image file,
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use a command similar to this:
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dtc -b 0 -f -I dts -O dtb bsc9132qds.dts > bsc9132qds.dtb
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Likely, that .dts file will come from here;
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linux-2.6/arch/powerpc/boot/dts/bsc9132qds.dts
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Booting Linux
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-------------
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Place a linux uImage in the TFTP disk area.
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tftp 1000000 uImage
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tftp 2000000 rootfs.ext2.gz.uboot
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tftp c00000 bsc9132qds.dtb
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bootm 1000000 2000000 c00000
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