/*
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* Copyright (C) ARM Ltd 2015
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*
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* Author: Liviu Dudau <Liviu.Dudau@arm.com>
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*
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* SPDX-Licence-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <linux/bitops.h>
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#include <pci_ids.h>
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#include "pcie.h"
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/* XpressRICH3 support */
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#define XR3_CONFIG_BASE 0x7ff30000
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#define XR3_RESET_BASE 0x7ff20000
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#define XR3_PCI_ECAM_START 0x40000000
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#define XR3_PCI_ECAM_SIZE 28 /* as power of 2 = 0x10000000 */
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#define XR3_PCI_IOSPACE_START 0x5f800000
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#define XR3_PCI_IOSPACE_SIZE 23 /* as power of 2 = 0x800000 */
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#define XR3_PCI_MEMSPACE_START 0x50000000
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#define XR3_PCI_MEMSPACE_SIZE 27 /* as power of 2 = 0x8000000 */
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#define XR3_PCI_MEMSPACE64_START 0x4000000000
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#define XR3_PCI_MEMSPACE64_SIZE 33 /* as power of 2 = 0x200000000 */
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#define JUNO_V2M_MSI_START 0x2c1c0000
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#define JUNO_V2M_MSI_SIZE 12 /* as power of 2 = 4096 */
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#define XR3PCI_BASIC_STATUS 0x18
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#define XR3PCI_BS_GEN_MASK (0xf << 8)
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#define XR3PCI_BS_LINK_MASK 0xff
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#define XR3PCI_VIRTCHAN_CREDITS 0x90
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#define XR3PCI_BRIDGE_PCI_IDS 0x9c
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#define XR3PCI_PEX_SPC2 0xd8
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#define XR3PCI_ATR_PCIE_WIN0 0x600
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#define XR3PCI_ATR_PCIE_WIN1 0x700
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#define XR3PCI_ATR_AXI4_SLV0 0x800
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#define XR3PCI_ATR_TABLE_SIZE 0x20
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#define XR3PCI_ATR_SRC_ADDR_LOW 0x0
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#define XR3PCI_ATR_SRC_ADDR_HIGH 0x4
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#define XR3PCI_ATR_TRSL_ADDR_LOW 0x8
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#define XR3PCI_ATR_TRSL_ADDR_HIGH 0xc
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#define XR3PCI_ATR_TRSL_PARAM 0x10
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/* IDs used in the XR3PCI_ATR_TRSL_PARAM */
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#define XR3PCI_ATR_TRSLID_AXIDEVICE (0x420004)
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#define XR3PCI_ATR_TRSLID_AXIMEMORY (0x4e0004) /* Write-through, read/write allocate */
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#define XR3PCI_ATR_TRSLID_PCIE_CONF (0x000001)
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#define XR3PCI_ATR_TRSLID_PCIE_IO (0x020000)
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#define XR3PCI_ATR_TRSLID_PCIE_MEMORY (0x000000)
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#define XR3PCI_ECAM_OFFSET(b, d, o) (((b) << 20) | \
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(PCI_SLOT(d) << 15) | \
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(PCI_FUNC(d) << 12) | o)
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#define JUNO_RESET_CTRL 0x1004
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#define JUNO_RESET_CTRL_PHY BIT(0)
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#define JUNO_RESET_CTRL_RC BIT(1)
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#define JUNO_RESET_STATUS 0x1008
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#define JUNO_RESET_STATUS_PLL BIT(0)
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#define JUNO_RESET_STATUS_PHY BIT(1)
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#define JUNO_RESET_STATUS_RC BIT(2)
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#define JUNO_RESET_STATUS_MASK (JUNO_RESET_STATUS_PLL | \
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JUNO_RESET_STATUS_PHY | \
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JUNO_RESET_STATUS_RC)
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void xr3pci_set_atr_entry(unsigned long base, unsigned long src_addr,
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unsigned long trsl_addr, int window_size,
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int trsl_param)
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{
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/* X3PCI_ATR_SRC_ADDR_LOW:
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- bit 0: enable entry,
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- bits 1-6: ATR window size: total size in bytes: 2^(ATR_WSIZE + 1)
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- bits 7-11: reserved
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- bits 12-31: start of source address
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*/
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writel((u32)(src_addr & 0xfffff000) | (window_size - 1) << 1 | 1,
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base + XR3PCI_ATR_SRC_ADDR_LOW);
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writel((u32)(src_addr >> 32), base + XR3PCI_ATR_SRC_ADDR_HIGH);
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writel((u32)(trsl_addr & 0xfffff000), base + XR3PCI_ATR_TRSL_ADDR_LOW);
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writel((u32)(trsl_addr >> 32), base + XR3PCI_ATR_TRSL_ADDR_HIGH);
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writel(trsl_param, base + XR3PCI_ATR_TRSL_PARAM);
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debug("ATR entry: 0x%010lx %s 0x%010lx [0x%010llx] (param: 0x%06x)\n",
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src_addr, (trsl_param & 0x400000) ? "<-" : "->", trsl_addr,
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((u64)1) << window_size, trsl_param);
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}
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void xr3pci_setup_atr(void)
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{
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/* setup PCIe to CPU address translation tables */
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unsigned long base = XR3_CONFIG_BASE + XR3PCI_ATR_PCIE_WIN0;
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/* forward all writes from PCIe to GIC V2M (used for MSI) */
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xr3pci_set_atr_entry(base, JUNO_V2M_MSI_START, JUNO_V2M_MSI_START,
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JUNO_V2M_MSI_SIZE, XR3PCI_ATR_TRSLID_AXIDEVICE);
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base += XR3PCI_ATR_TABLE_SIZE;
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/* PCIe devices can write anywhere in memory */
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xr3pci_set_atr_entry(base, PHYS_SDRAM_1, PHYS_SDRAM_1,
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31 /* grant access to all RAM under 4GB */,
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XR3PCI_ATR_TRSLID_AXIMEMORY);
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base += XR3PCI_ATR_TABLE_SIZE;
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xr3pci_set_atr_entry(base, PHYS_SDRAM_2, PHYS_SDRAM_2,
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XR3_PCI_MEMSPACE64_SIZE,
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XR3PCI_ATR_TRSLID_AXIMEMORY);
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/* setup CPU to PCIe address translation table */
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base = XR3_CONFIG_BASE + XR3PCI_ATR_AXI4_SLV0;
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/* setup ECAM space to bus configuration interface */
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xr3pci_set_atr_entry(base, XR3_PCI_ECAM_START, 0, XR3_PCI_ECAM_SIZE,
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XR3PCI_ATR_TRSLID_PCIE_CONF);
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base += XR3PCI_ATR_TABLE_SIZE;
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/* setup IO space translation */
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xr3pci_set_atr_entry(base, XR3_PCI_IOSPACE_START, 0,
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XR3_PCI_IOSPACE_SIZE, XR3PCI_ATR_TRSLID_PCIE_IO);
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base += XR3PCI_ATR_TABLE_SIZE;
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/* setup 32bit MEM space translation */
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xr3pci_set_atr_entry(base, XR3_PCI_MEMSPACE_START, XR3_PCI_MEMSPACE_START,
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XR3_PCI_MEMSPACE_SIZE, XR3PCI_ATR_TRSLID_PCIE_MEMORY);
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base += XR3PCI_ATR_TABLE_SIZE;
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/* setup 64bit MEM space translation */
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xr3pci_set_atr_entry(base, XR3_PCI_MEMSPACE64_START, XR3_PCI_MEMSPACE64_START,
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XR3_PCI_MEMSPACE64_SIZE, XR3PCI_ATR_TRSLID_PCIE_MEMORY);
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}
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void xr3pci_init(void)
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{
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u32 val;
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int timeout = 200;
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/* Initialise the XpressRICH3 PCIe host bridge */
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/* add credits */
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writel(0x00f0b818, XR3_CONFIG_BASE + XR3PCI_VIRTCHAN_CREDITS);
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writel(0x1, XR3_CONFIG_BASE + XR3PCI_VIRTCHAN_CREDITS + 4);
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/* allow ECRC */
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writel(0x6006, XR3_CONFIG_BASE + XR3PCI_PEX_SPC2);
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/* setup the correct class code for the host bridge */
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writel(PCI_CLASS_BRIDGE_PCI << 16, XR3_CONFIG_BASE + XR3PCI_BRIDGE_PCI_IDS);
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/* reset phy and root complex */
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writel(JUNO_RESET_CTRL_PHY | JUNO_RESET_CTRL_RC,
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XR3_RESET_BASE + JUNO_RESET_CTRL);
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do {
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mdelay(1);
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val = readl(XR3_RESET_BASE + JUNO_RESET_STATUS);
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} while (--timeout &&
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(val & JUNO_RESET_STATUS_MASK) != JUNO_RESET_STATUS_MASK);
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if (!timeout) {
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printf("PCI XR3 Root complex reset timed out\n");
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return;
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}
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/* Wait for the link to train */
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mdelay(20);
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timeout = 20;
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do {
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mdelay(1);
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val = readl(XR3_CONFIG_BASE + XR3PCI_BASIC_STATUS);
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} while (--timeout && !(val & XR3PCI_BS_LINK_MASK));
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if (!(val & XR3PCI_BS_LINK_MASK)) {
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printf("Failed to negotiate a link!\n");
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return;
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}
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printf("PCIe XR3 Host Bridge enabled: x%d link (Gen %d)\n",
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val & XR3PCI_BS_LINK_MASK, (val & XR3PCI_BS_GEN_MASK) >> 8);
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xr3pci_setup_atr();
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}
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void vexpress64_pcie_init(void)
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{
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xr3pci_init();
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}
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