/*
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* (C) Copyright 2019 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <boot_rkimg.h>
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#include <dm.h>
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#include <malloc.h>
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#include <of_live.h>
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#include <dm/device-internal.h>
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#include <dm/root.h>
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#include <dm/uclass-internal.h>
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#include <asm/arch/hotkey.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_USING_KERNEL_DTB_V2
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static int dm_rm_kernel_dev(void)
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{
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struct udevice *dev, *rec[10];
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u32 uclass[] = { UCLASS_CRYPTO };
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int i, j, k;
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for (i = 0, j = 0; i < ARRAY_SIZE(uclass); i++) {
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for (uclass_find_first_device(uclass[i], &dev); dev;
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uclass_find_next_device(&dev)) {
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if (dev->flags & DM_FLAG_KNRL_DTB)
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rec[j++] = dev;
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}
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for (k = 0; k < j; k++) {
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device_remove(rec[k], DM_REMOVE_NORMAL);
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device_unbind(rec[k]);
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}
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}
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return 0;
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}
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static int dm_rm_u_boot_dev(void)
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{
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struct udevice *dev, *rec[10];
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u32 uclass[] = { UCLASS_ETH };
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int del = 0;
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int i, j, k;
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for (i = 0, j = 0; i < ARRAY_SIZE(uclass); i++) {
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for (uclass_find_first_device(uclass[i], &dev); dev;
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uclass_find_next_device(&dev)) {
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if (dev->flags & DM_FLAG_KNRL_DTB)
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del = 1;
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else
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rec[j++] = dev;
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}
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/* remove u-boot dev if there is someone from kernel */
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if (del) {
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for (k = 0; k < j; k++) {
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device_remove(rec[k], DM_REMOVE_NORMAL);
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device_unbind(rec[k]);
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}
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}
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}
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return 0;
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}
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#else
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/* Here, only fixup cru phandle, pmucru is not included */
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static int phandles_fixup_cru(const void *fdt)
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{
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const char *props[] = { "clocks", "assigned-clocks", "resets"};
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struct udevice *dev;
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struct uclass *uc;
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const char *comp;
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u32 id, nclocks;
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u32 *clocks;
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int phandle, ncells;
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int off, offset;
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int ret, length;
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int i, j;
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int first_phandle = -1;
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phandle = -ENODATA;
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ncells = -ENODATA;
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/* fdt points to kernel dtb, getting cru phandle and "#clock-cells" */
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for (offset = fdt_next_node(fdt, 0, NULL);
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offset >= 0;
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offset = fdt_next_node(fdt, offset, NULL)) {
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comp = fdt_getprop(fdt, offset, "compatible", NULL);
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if (!comp)
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continue;
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/* Actually, this is not a good method to get cru node */
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off = strlen(comp) - strlen("-cru");
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if (off > 0 && !strncmp(comp + off, "-cru", 4)) {
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phandle = fdt_get_phandle(fdt, offset);
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ncells = fdtdec_get_int(fdt, offset,
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"#clock-cells", -ENODATA);
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break;
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}
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}
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if (phandle == -ENODATA || ncells == -ENODATA)
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return 0;
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debug("%s: target cru: clock-cells:%d, phandle:0x%x\n",
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__func__, ncells, fdt32_to_cpu(phandle));
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/* Try to fixup all cru phandle from U-Boot dtb nodes */
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for (id = 0; id < UCLASS_COUNT; id++) {
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ret = uclass_get(id, &uc);
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if (ret)
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continue;
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if (list_empty(&uc->dev_head))
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continue;
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list_for_each_entry(dev, &uc->dev_head, uclass_node) {
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/* Only U-Boot node go further */
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if (!dev_read_bool(dev, "u-boot,dm-pre-reloc") &&
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!dev_read_bool(dev, "u-boot,dm-spl"))
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continue;
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for (i = 0; i < ARRAY_SIZE(props); i++) {
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if (!dev_read_prop(dev, props[i], &length))
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continue;
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clocks = malloc(length);
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if (!clocks)
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return -ENOMEM;
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/* Read "props[]" which contains cru phandle */
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nclocks = length / sizeof(u32);
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if (dev_read_u32_array(dev, props[i],
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clocks, nclocks)) {
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free(clocks);
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continue;
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}
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/* Fixup with kernel cru phandle */
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for (j = 0; j < nclocks; j += (ncells + 1)) {
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/*
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* Check: update pmucru phandle with cru
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* phandle by mistake.
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*/
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if (first_phandle == -1)
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first_phandle = clocks[j];
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if (clocks[j] != first_phandle) {
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debug("WARN: %s: first cru phandle=%d, this=%d\n",
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dev_read_name(dev),
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first_phandle, clocks[j]);
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continue;
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}
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clocks[j] = phandle;
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}
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/*
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* Override live dt nodes but not fdt nodes,
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* because all U-Boot nodes has been imported
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* to live dt nodes, should use "dev_xxx()".
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*/
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dev_write_u32_array(dev, props[i],
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clocks, nclocks);
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free(clocks);
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}
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}
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}
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return 0;
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}
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static int phandles_fixup_gpio(const void *fdt, void *ufdt)
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{
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struct udevice *dev;
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struct uclass *uc;
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const char *prop = "gpios";
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const char *comp;
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char *gpio_name[10];
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int gpio_off[10];
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int pinctrl;
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int offset;
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int i = 0;
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int n = 0;
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pinctrl = fdt_path_offset(fdt, "/pinctrl");
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if (pinctrl < 0)
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return 0;
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memset(gpio_name, 0, sizeof(gpio_name));
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for (offset = fdt_first_subnode(fdt, pinctrl);
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offset >= 0;
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offset = fdt_next_subnode(fdt, offset)) {
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/* assume the font nodes are gpio node */
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if (++i >= ARRAY_SIZE(gpio_name))
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break;
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comp = fdt_getprop(fdt, offset, "compatible", NULL);
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if (!comp)
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continue;
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if (!strcmp(comp, "rockchip,gpio-bank")) {
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gpio_name[n] = (char *)fdt_get_name(fdt, offset, NULL);
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gpio_off[n] = offset;
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n++;
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}
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}
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if (!gpio_name[0])
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return 0;
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if (uclass_get(UCLASS_KEY, &uc) || list_empty(&uc->dev_head))
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return 0;
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list_for_each_entry(dev, &uc->dev_head, uclass_node) {
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u32 new_phd, phd_old;
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char *name;
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ofnode ofn;
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if (!dev_read_bool(dev, "u-boot,dm-pre-reloc") &&
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!dev_read_bool(dev, "u-boot,dm-spl"))
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continue;
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if (dev_read_u32_array(dev, prop, &phd_old, 1))
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continue;
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ofn = ofnode_get_by_phandle(phd_old);
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if (!ofnode_valid(ofn))
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continue;
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name = (char *)ofnode_get_name(ofn);
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if (!name)
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continue;
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for (i = 0; i < ARRAY_SIZE(gpio_name); i++) {
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if (gpio_name[i] && !strcmp(name, gpio_name[i])) {
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new_phd = fdt_get_phandle(fdt, gpio_off[i]);
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dev_write_u32_array(dev, prop, &new_phd, 1);
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break;
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}
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}
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}
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return 0;
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}
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#endif
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__weak int board_mmc_dm_reinit(struct udevice *dev)
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{
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return 0;
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}
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static int mmc_dm_reinit(void)
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{
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struct udevice *dev;
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struct uclass *uc;
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int ret;
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if (uclass_get(UCLASS_MMC, &uc) || list_empty(&uc->dev_head))
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return 0;
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list_for_each_entry(dev, &uc->dev_head, uclass_node) {
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ret = board_mmc_dm_reinit(dev);
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if (ret)
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return ret;
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}
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return 0;
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}
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/* Check by property: "/compatible" */
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static int dtb_check_ok(void *kfdt, void *ufdt)
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{
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const char *compat;
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int index;
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/* TODO */
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return 1;
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for (index = 0;
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compat = fdt_stringlist_get(ufdt, 0, "compatible",
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index, NULL), compat;
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index++) {
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debug("u-compat: %s\n", compat);
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if (!fdt_node_check_compatible(kfdt, 0, compat))
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return 1;
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}
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return 0;
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}
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int init_kernel_dtb(void)
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{
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#ifndef CONFIG_USING_KERNEL_DTB_V2
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void *ufdt_blob = (void *)gd->fdt_blob;
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#endif
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ulong fdt_addr = 0;
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int ret = -ENODEV;
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printf("DM: v%d\n", IS_ENABLED(CONFIG_USING_KERNEL_DTB_V2) ? 2 : 1);
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/*
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* If memory size <= 128MB, we firstly try to get "fdt_addr1_r".
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*/
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if (gd->ram_size <= SZ_128M)
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fdt_addr = env_get_ulong("fdt_addr1_r", 16, 0);
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if (!fdt_addr)
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fdt_addr = env_get_ulong("fdt_addr_r", 16, 0);
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if (!fdt_addr) {
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printf("No Found FDT Load Address.\n");
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return -ENODEV;
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}
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if (IS_ENABLED(CONFIG_EMBED_KERNEL_DTB_ALWAYS)) {
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printf("Always embed kernel dtb\n");
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goto dtb_embed;
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}
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ret = rockchip_read_dtb_file((void *)fdt_addr);
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if (!ret) {
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if (!dtb_check_ok((void *)fdt_addr, (void *)gd->fdt_blob)) {
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ret = -EINVAL;
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printf("Kernel dtb mismatch this platform!\n");
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} else {
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goto dtb_okay;
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}
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}
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dtb_embed:
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if (gd->fdt_blob_kern) {
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if (!dtb_check_ok((void *)gd->fdt_blob_kern, (void *)gd->fdt_blob)) {
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printf("Embedded kernel dtb mismatch this platform!\n");
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return -EINVAL;
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}
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fdt_addr = (ulong)memalign(ARCH_DMA_MINALIGN,
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fdt_totalsize(gd->fdt_blob_kern));
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if (!fdt_addr)
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return -ENOMEM;
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/*
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* Alloc another space for this embed kernel dtb.
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* Because "fdt_addr_r" *MUST* be the fdt passed to kernel.
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*/
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memcpy((void *)fdt_addr, gd->fdt_blob_kern,
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fdt_totalsize(gd->fdt_blob_kern));
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printf("DTB: %s\n", CONFIG_EMBED_KERNEL_DTB_PATH);
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} else {
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printf("Failed to get kernel dtb, ret=%d\n", ret);
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return -ENOENT;
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}
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dtb_okay:
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gd->fdt_blob = (void *)fdt_addr;
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hotkey_run(HK_FDT);
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#ifndef CONFIG_USING_KERNEL_DTB_V2
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/*
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* There is a phandle miss match between U-Boot and kernel dtb node,
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* we fixup it in U-Boot live dt nodes.
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*
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* CRU: all nodes.
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* GPIO: key nodes.
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*/
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phandles_fixup_cru((void *)gd->fdt_blob);
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phandles_fixup_gpio((void *)gd->fdt_blob, (void *)ufdt_blob);
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#endif
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gd->flags |= GD_FLG_KDTB_READY;
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gd->of_root_f = gd->of_root;
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of_live_build((void *)gd->fdt_blob, (struct device_node **)&gd->of_root);
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dm_scan_fdt((void *)gd->fdt_blob, false);
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#ifdef CONFIG_USING_KERNEL_DTB_V2
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dm_rm_kernel_dev();
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dm_rm_u_boot_dev();
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#endif
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/*
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* There maybe something for the mmc devices to do after kernel dtb
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* dm setup, eg: regain the clock device binding from kernel dtb.
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*/
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mmc_dm_reinit();
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/* Reserve 'reserved-memory' */
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ret = boot_fdt_add_sysmem_rsv_regions((void *)gd->fdt_blob);
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if (ret)
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return ret;
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return 0;
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}
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