/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2023 Rockchip Electronics Co., Ltd
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*
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*/
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#ifndef _SPL_DISPLAY_H_
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#define _SPL_DISPLAY_H_
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#include <common.h>
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#include <drm_modes.h>
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#include <mp_boot.h>
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/* SPL display */
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#define RK3528_VOP_BASE 0xff840000
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#define RK3528_HDMI_BASE 0xff8d0000
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#define RK3528_HDMIPHY_BASE 0xffe00000
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#define RK3528_CRU_BASE 0xff4a0000
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#define RK3528_GPIO0_IOC_BASE 0xff540000
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#define RK3528_GPIO_BASE 0xff610000
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struct spl_display_info {
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struct drm_display_mode mode;
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u32 bus_format;
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u32 enabled;
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};
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#endif
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