/*
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* This header provides macros for at91 dma bindings.
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*
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* Copyright (C) 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
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*
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* GPLv2 only
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*/
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#ifndef __DT_BINDINGS_AT91_DMA_H__
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#define __DT_BINDINGS_AT91_DMA_H__
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/* ---------- HDMAC ---------- */
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/*
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* Source and/or destination peripheral ID
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*/
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#define AT91_DMA_CFG_PER_ID_MASK (0xff)
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#define AT91_DMA_CFG_PER_ID(id) (id & AT91_DMA_CFG_PER_ID_MASK)
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/*
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* FIFO configuration: it defines when a request is serviced.
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*/
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#define AT91_DMA_CFG_FIFOCFG_OFFSET (8)
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#define AT91_DMA_CFG_FIFOCFG_MASK (0xf << AT91_DMA_CFG_FIFOCFG_OFFSET)
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#define AT91_DMA_CFG_FIFOCFG_HALF (0x0 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* half FIFO (default behavior) */
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#define AT91_DMA_CFG_FIFOCFG_ALAP (0x1 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* largest defined AHB burst */
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#define AT91_DMA_CFG_FIFOCFG_ASAP (0x2 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* single AHB access */
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/* ---------- XDMAC ---------- */
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#define AT91_XDMAC_DT_MEM_IF_MASK (0x1)
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#define AT91_XDMAC_DT_MEM_IF_OFFSET (13)
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#define AT91_XDMAC_DT_MEM_IF(mem_if) (((mem_if) & AT91_XDMAC_DT_MEM_IF_MASK) \
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<< AT91_XDMAC_DT_MEM_IF_OFFSET)
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#define AT91_XDMAC_DT_GET_MEM_IF(cfg) (((cfg) >> AT91_XDMAC_DT_MEM_IF_OFFSET) \
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& AT91_XDMAC_DT_MEM_IF_MASK)
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#define AT91_XDMAC_DT_PER_IF_MASK (0x1)
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#define AT91_XDMAC_DT_PER_IF_OFFSET (14)
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#define AT91_XDMAC_DT_PER_IF(per_if) (((per_if) & AT91_XDMAC_DT_PER_IF_MASK) \
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<< AT91_XDMAC_DT_PER_IF_OFFSET)
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#define AT91_XDMAC_DT_GET_PER_IF(cfg) (((cfg) >> AT91_XDMAC_DT_PER_IF_OFFSET) \
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& AT91_XDMAC_DT_PER_IF_MASK)
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#define AT91_XDMAC_DT_PERID_MASK (0x7f)
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#define AT91_XDMAC_DT_PERID_OFFSET (24)
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#define AT91_XDMAC_DT_PERID(perid) (((perid) & AT91_XDMAC_DT_PERID_MASK) \
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<< AT91_XDMAC_DT_PERID_OFFSET)
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#define AT91_XDMAC_DT_GET_PERID(cfg) (((cfg) >> AT91_XDMAC_DT_PERID_OFFSET) \
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& AT91_XDMAC_DT_PERID_MASK)
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#endif /* __DT_BINDINGS_AT91_DMA_H__ */
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