/*
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* atmel_lcd.h - Atmel LCD Controller structures
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*
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* (C) Copyright 2001
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ATMEL_LCD_H_
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#define _ATMEL_LCD_H_
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/**
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* struct atmel_lcd_platdata - platform data for Atmel LCDs with driver model
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*
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* @timing_index: Index of LCD timing to use in device tree node
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*/
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struct atmel_lcd_platdata {
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int timing_index;
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};
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typedef struct vidinfo {
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ushort vl_col; /* Number of columns (i.e. 640) */
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ushort vl_row; /* Number of rows (i.e. 480) */
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ushort vl_rot; /* Rotation of Display (0, 1, 2, 3) */
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u_long vl_clk; /* pixel clock in ps */
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/* LCD configuration register */
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u_long vl_sync; /* Horizontal / vertical sync */
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u_long vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */
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u_long vl_tft; /* 0 = passive, 1 = TFT */
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u_long vl_cont_pol_low; /* contrast polarity is low */
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u_long vl_clk_pol; /* clock polarity */
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/* Horizontal control register. */
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u_long vl_hsync_len; /* Length of horizontal sync */
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u_long vl_left_margin; /* Time from sync to picture */
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u_long vl_right_margin; /* Time from picture to sync */
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/* Vertical control register. */
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u_long vl_vsync_len; /* Length of vertical sync */
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u_long vl_upper_margin; /* Time from sync to picture */
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u_long vl_lower_margin; /* Time from picture to sync */
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u_long mmio; /* Memory mapped registers */
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} vidinfo_t;
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#endif
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