/*
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* Header providing constants for Rockchip suspend bindings.
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*
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* Copyright (C) 2018, Fuzhou Rockchip Electronics Co., Ltd
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* Author: Joseph Chen
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __DT_BINDINGS_RK3308_PM_H__
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#define __DT_BINDINGS_RK3308_PM_H__
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/******************************bits ops************************************/
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#ifndef BIT
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#define BIT(nr) (1 << (nr))
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#endif
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/*
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* RK3308 system suspend mode configure definitions.
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*
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* Driver:
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* These configures are pass to ATF by SMC in:
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* drivers/soc/rockchip/rockchip_pm_config.c
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*
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* DTS:
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* rockchip_suspend: rockchip-suspend {
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* rockchip,sleep-mode-config = <...>;
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* rockchip,wakeup-config = <...>;
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* rockchip,apios-suspend = <...>;
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* rockchip,pwm-regulator-config = <...>;
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* };
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*/
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/*
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* Suspend mode:
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* rockchip,sleep-mode-config = <...>;
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*/
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#define RKPM_ARMOFF BIT(0) /* vdd_arm off */
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#define RKPM_VADOFF BIT(1) /* assume vad off, enter lowest system suspend */
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#define RKPM_PMU_HW_PLLS_PD BIT(3) /* disable PLLs by PMU hardware, recommend */
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#define RKPM_PMU_DIS_OSC BIT(4) /* disable 24M osc */
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#define RKPM_PMU_PMUALIVE_32K BIT(5) /* pvtm 32khz */
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#define RKPM_PMU_EXT_32K BIT(6) /* ext 32khz osc */
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#define RKPM_DDR_SREF_HARDWARE BIT(7) /* ddr enter self-refresh by PMU hardware, not recommend */
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#define RKPM_DDR_EXIT_SRPD_IDLE BIT(8) /* ddr exit sr/pd idle by ddr controller, not recommend */
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#define RKPM_PDM_CLK_OFF BIT(9) /* armoff with pdm clk off, not recommend */
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#define RKPM_PWM_VOLTAGE_DEFAULT BIT(10) /* pwm regulator default voltage (same with maskrom) */
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#define RKPM_PWM_VOLTAGE_DEFAULT_BS BIT(20) /* pwm regulator default voltage on 0.895v for RK3308BS chip */
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/*
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* Regulator mode:
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* rockchip,pwm-regulator-config = <...>;
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*/
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#define RKPM_PWM_REGULATOR BIT(2) /* support pwm regulator */
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/*
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* Wakeup source:
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* rockchip,wakeup-config = <...>;
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*/
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#define RKPM_ARM_PRE_WAKEUP_EN BIT(11) /* all interrupts can wakeup(gic doesn't filter these) */
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#define RKPM_ARM_GIC_WAKEUP_EN BIT(12) /* all interrupts can wakeup(gic filter these) */
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#define RKPM_SDMMC_WAKEUP_EN BIT(13) /* sdmmc can wakeup */
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#define RKPM_SDMMC_GRF_IRQ_WAKEUP_EN BIT(14) /* sdmmc grf irq can wakeup */
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#define RKPM_TIMER_WAKEUP_EN BIT(15) /* rk timers can wakeup */
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#define RKPM_USBDEV_WAKEUP_EN BIT(16) /* usbdev can wakeup */
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#define RKPM_TIMEOUT_WAKEUP_EN BIT(17) /* PMU timeout can wakeup, for self test */
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#define RKPM_GPIO0_WAKEUP_EN BIT(18) /* gpio0(only) can wakeup */
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#define RKPM_VAD_WAKEUP_EN BIT(19) /* vad can wakeup */
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/*
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* Debug control in system suspend:
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* rockchip,sleep-mode-config = <...>;
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*/
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#define RKPM_DBG_INT_TIMER_TEST BIT(22) /* enable RKPM_TIMEOUT_WAKEUP_EN */
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#define RKPM_DBG_WOARKAROUND BIT(23) /* ignore, useless */
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#define RKPM_DBG_VAD_INT_OFF BIT(24) /* enable RKPM_VADOFF */
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#define RKPM_DBG_CLK_UNGATE BIT(25) /* enable all clks */
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#define RKPM_DBG_CLKOUT BIT(26) /* enable test_out clk output */
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#define RKPM_DBG_FSM_SOUT BIT(27) /* FSM state one pin out */
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#define RKPM_DBG_FSM_STATE BIT(28) /* FSM state multi pins out */
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#define RKPM_DBG_REG BIT(29) /* verbose regs */
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#define RKPM_DBG_VERBOSE BIT(30) /* verbose more message */
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#define RKPM_CONFIG_WAKEUP_END BIT(31) /* ignore, it's a placeholder */
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/*
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* GPIOn/PWMn ignore global 1st reset, usually used for pwr_hold pin:
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* rockchip,apios-suspend = <...>;
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*/
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#define GLB1RST_IGNORE_PWM0 BIT(23) /* pwm0 ignore global 1st reset */
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#define GLB1RST_IGNORE_PWM1 BIT(24) /* pwm1 ignore global 1st reset */
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#define GLB1RST_IGNORE_PWM2 BIT(25) /* pwm2 ignore global 1st reset */
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#define GLB1RST_IGNORE_GPIO0 BIT(26) /* gpio0 ignore global 1st reset */
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#define GLB1RST_IGNORE_GPIO1 BIT(27) /* gpio1 ignore global 1st reset */
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#define GLB1RST_IGNORE_GPIO2 BIT(28) /* gpio2 ignore global 1st reset */
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#define GLB1RST_IGNORE_GPIO3 BIT(29) /* gpio3 ignore global 1st reset */
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#define GLB1RST_IGNORE_GPIO4 BIT(30) /* gpio4 ignore global 1st reset */
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#endif
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