/*
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* Header providing constants for Rockchip suspend bindings.
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*
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* Copyright (C) 2017, Fuzhou Rockchip Electronics Co., Ltd
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* Author: Power.xu
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __DT_BINDINGS_SUSPEND_ROCKCHIP_RK3288_H__
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#define __DT_BINDINGS_SUSPEND_ROCKCHIP_RK3288_H__
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/* the suspend mode */
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#define RKPM_CTR_PWR_DMNS (1 << 0)
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#define RKPM_CTR_GTCLKS (1 << 1)
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#define RKPM_CTR_PLLS (1 << 2)
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#define RKPM_CTR_VOLTS (1 << 3)
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#define RKPM_CTR_GPIOS (1 << 4)
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#define RKPM_CTR_DDR (1 << 5)
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#define RKPM_CTR_PMIC (1 << 6)
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/* system clk is 24M,and div to min */
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#define RKPM_CTR_SYSCLK_DIV (1 << 7)
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/* switch sysclk to 32k, need hardwart support, and div to min */
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#define RKPM_CTR_SYSCLK_32K (1 << 8)
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/* switch sysclk to 32k,disable 24M OSC,
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* need hardwart susport. and div to min
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*/
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#define RKPM_CTR_SYSCLK_OSC_DIS (1 << 9)
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#define RKPM_CTR_BUS_IDLE (1 << 14)
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#define RKPM_CTR_SRAM (1 << 15)
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/*Low Power Function Selection*/
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#define RKPM_CTR_IDLESRAM_MD (1 << 16)
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#define RKPM_CTR_IDLEAUTO_MD (1 << 17)
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#define RKPM_CTR_ARMDP_LPMD (1 << 18)
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#define RKPM_CTR_ARMOFF_LPMD (1 << 19)
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#define RKPM_CTR_ARMLOGDP_LPMD (1 << 20)
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#define RKPM_CTR_ARMOFF_LOGDP_LPMD (1 << 21)
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#define RKPM_CTR_ARMLOGOFF_DLPMD (1 << 22)
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/* the wake up source */
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#define RKPM_ARMINT_WKUP_EN (1 << 0)
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#define RKPM_SDMMC_WKUP_EN (1 << 2)
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#define RKPM_GPIO_WKUP_EN (1 << 3)
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/* the pwm regulator */
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#define PWM0_REGULATOR_EN (1 << 0)
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#define PWM1_REGULATOR_EN (1 << 1)
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#define PWM2_REGULATOR_EN (1 << 2)
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#define PWM3_REGULATOR_EN (1 << 3)
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#endif
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