/*
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* Header providing constants for Rockchip suspend bindings.
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*
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* Copyright (C) 2017, Fuzhou Rockchip Electronics Co., Ltd
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* Author: XiaoDong.Huang
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __DT_BINDINGS_SUSPEND_ROCKCHIP_RK322X_H__
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#define __DT_BINDINGS_SUSPEND_ROCKCHIP_RK322X_H__
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#ifndef BIT
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#define BIT(nr) (1 << (nr))
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#endif
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/* the suspend mode */
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#define RKPM_CTR_PWR_DMNS BIT(0)
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#define RKPM_CTR_GTCLKS BIT(1)
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#define RKPM_CTR_PLLS BIT(2)
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#define RKPM_CTR_VOLTS BIT(3)
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#define RKPM_CTR_GPIOS BIT(4)
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#define RKPM_CTR_DDR BIT(5)
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#define RKPM_CTR_PMIC BIT(6)
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/* system clk is 24M,and div to min */
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#define RKPM_CTR_SYSCLK_DIV BIT(7)
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/* switch sysclk to 32k, need hardwart support, and div to min */
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#define RKPM_CTR_SYSCLK_32K BIT(8)
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/* switch sysclk to 32k,disable 24M OSC,
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* need hardwart susport. and div to min
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*/
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#define RKPM_CTR_SYSCLK_OSC_DIS BIT(9)
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#define RKPM_CTR_VOL_PWM0 BIT(10)
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#define RKPM_CTR_VOL_PWM1 BIT(11)
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#define RKPM_CTR_VOL_PWM2 BIT(12)
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#define RKPM_CTR_VOL_PWM3 BIT(13)
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#define RKPM_CTR_BUS_IDLE BIT(14)
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#define RKPM_CTR_SRAM BIT(15)
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/*Low Power Function Selection*/
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#define RKPM_CTR_IDLESRAM_MD BIT(16)
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#define RKPM_CTR_IDLEAUTO_MD BIT(17)
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#define RKPM_CTR_ARMDP_LPMD BIT(18)
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#define RKPM_CTR_ARMOFF_LPMD BIT(19)
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#define RKPM_CTR_ARMLOGDP_LPMD BIT(20)
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#define RKPM_CTR_ARMOFF_LOGDP_LPMD BIT(21)
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#define RKPM_CTR_ARMLOGOFF_DLPMD BIT(22)
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#endif
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